1  /* Verify that overloaded built-ins for vec_extract() with long long
       2     inputs produce the right code with a P8 (LE or BE) target.  */
       3  
       4  /* { dg-do compile } */
       5  /* { dg-require-effective-target powerpc_vsx_ok } */
       6  /* { dg-options "-mdejagnu-cpu=power7 -O2" } */
       7  
       8  // Targeting P7. six tests total.
       9  // P7 (m64) with constants: xxpermdi, stfd, ld
      10  // P7 (m64) with variables: li, addi, stxvd2x, rldic, addi, ldx
      11  
      12  // P7 (m32) with constants: [xxpermdi or li/lwz,li/lwz],stxvw4x/stfd,lwz,lwz, addi
      13  // P7 (m32) with variables: li, addi/rlwinm, stxvd2x, rldic, addi/add, ldx/lwz
      14  
      15  /* results. */
      16  /* { dg-final { scan-assembler-times {\mstfd\M} 3 { target lp64 } } } */
      17  /* -m32 target with constant test has a stxvw4x in place of a stfd. */
      18  /* { dg-final { scan-assembler-times {\mstfd\M} 2 { target ilp32 } } } */
      19  /* { dg-final { scan-assembler-times {\mld\M} 3 { target lp64 } } } */
      20  /* { dg-final { scan-assembler-times {\mlwz\M} 11 { target ilp32 } } } */
      21  /* { dg-final { scan-assembler-times {\mli\M} 3 { target lp64 } } } */
      22  /* -m32 target with constant test uses (+2)li where the -m64 has an ld */
      23  /* { dg-final { scan-assembler-times {\mli\M} 5 { target ilp32 } } } */
      24  /* { dg-final { scan-assembler-times {\maddi\M} 6 { target lp64 } } } */
      25  /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M} 3 } } */
      26  /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
      27  /* { dg-final { scan-assembler-times {\mldx\M} 3 { target lp64 } } } */
      28  
      29  
      30  #include <altivec.h>
      31  
      32  unsigned long long
      33  testbl_var (vector bool long long vbl2, signed int si)
      34  {
      35    return vec_extract (vbl2, si);
      36  }
      37  
      38  signed long long
      39  testsl_var (vector signed long long vsl2, signed int si)
      40  {
      41    return vec_extract (vsl2, si);
      42  }
      43  
      44  unsigned long long
      45  testul_var (vector unsigned long long vul2, signed int si)
      46  {
      47    return vec_extract (vul2, si);
      48  }
      49  
      50  unsigned long long
      51  testbl_cst (vector bool long long vbl2)
      52  {
      53    return vec_extract (vbl2, 1);
      54  }
      55  
      56  signed long long
      57  testsl_cst (vector signed long long vsl2)
      58  {
      59    return vec_extract (vsl2, 1);
      60  }
      61  
      62  unsigned long long
      63  testul_cst (vector unsigned long vul2)
      64  {
      65    return vec_extract (vul2, 1);
      66  }
      67