1  /* { dg-do compile { target lp64 } } */
       2  /* { dg-skip-if "" { powerpc*-*-darwin* } } */
       3  /* { dg-require-effective-target powerpc_p8vector_ok } */
       4  /* { dg-options "-mpower8-vector -O2" } */
       5  
       6  /* Test that we generate XSCVDPSP instead of FRSP and XSCVDPSPN when we combine
       7     a round from double to float and moving the float value to a GPR.  */
       8  
       9  union u {
      10    float f;
      11    unsigned int ui;
      12    int si;
      13  };
      14  
      15  unsigned int
      16  ui_d (double d)
      17  {
      18    union u x;
      19    x.f = d;
      20    return x.ui;
      21  }
      22  
      23  /* { dg-final { scan-assembler     {\mmfvsrwz\M}   } } */
      24  /* { dg-final { scan-assembler     {\mxscvdpsp\M}  } } */
      25  /* { dg-final { scan-assembler-not {\mmfvsrd\M}    } } */
      26  /* { dg-final { scan-assembler-not {\mmtvsrwz\M}   } } */
      27  /* { dg-final { scan-assembler-not {\mmtvsrd\M}    } } */
      28  /* { dg-final { scan-assembler-not {\mxscvdpspn\M} } } */
      29  /* { dg-final { scan-assembler-not {\msrdi\M}      } } */