1  /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
       2  /* { dg-require-effective-target powerpc_p9vector_ok } */
       3  /* { dg-options "-mdejagnu-cpu=power9 -O2" } */
       4  
       5  #ifndef TYPE
       6  #define TYPE vector double
       7  #endif
       8  
       9  struct foo {
      10    TYPE a, b, c, d;
      11  };
      12  
      13  /* Test whether ISA 3.0 vector d-form instructions are implemented.  */
      14  void
      15  add (struct foo *p)
      16  {
      17    p->b = p->c + p->d;
      18  }
      19  
      20  /* Make sure we don't use direct moves to get stuff into GPR registers.  */
      21  void
      22  gpr (struct foo *p)
      23  {
      24    TYPE x = p->c;
      25  
      26    __asm__ (" # reg = %0" : "+r" (x));
      27  
      28    p->b = x;
      29  }
      30  
      31  /* { dg-final { scan-assembler     "lxv "      } } */
      32  /* { dg-final { scan-assembler     "stxv "     } } */
      33  /* { dg-final { scan-assembler-not "lxvx "     } } */
      34  /* { dg-final { scan-assembler-not "stxvx "    } } */
      35  /* { dg-final { scan-assembler-not "mfvsrd "   } } */
      36  /* { dg-final { scan-assembler-not "mfvsrld "  } } */
      37  /* { dg-final { scan-assembler     "l\[dq\] "  } } */
      38  /* { dg-final { scan-assembler     "st\[dq\] " } } */