1  /* { dg-do compile { target { lp64 } } } */
       2  /* { dg-require-effective-target power10_ok } */
       3  /* { dg-options "-O2 -mdejagnu-cpu=power10" } */
       4  
       5  /* This tests whether GCC generates the ISA 3.1 BRW byte swap instruction for
       6     GPR data, but generates XXBRW for data in a vector register.  */
       7  
       8  unsigned long long
       9  bswap_ll (unsigned long long a)
      10  {
      11    return __builtin_bswap64 (a); /* { dg-final { scan-assembler {\mbrd\M} } } */
      12  }
      13  
      14  double
      15  bswap_ll_dbl (unsigned long long a)
      16  {
      17    unsigned int b = a;
      18    /* Force the value to be loaded into a vector register.  */
      19    __asm__ (" # %x0" : "+wa" (b));
      20  
      21    /* { dg-final { scan-assembler {\mxxbrd\M} } } */
      22    return (double) __builtin_bswap64 (b);
      23  }