1  /* { dg-do compile } */
       2  /* { dg-options "-O2 -march=r2 -mno-cache-volatile" } */
       3  /* { dg-final { scan-assembler-times "addi\tr., r., %lo" 12 } } */
       4  /* { dg-final { scan-assembler-not "ldw\t" } } */
       5  /* { dg-final { scan-assembler-not "stw\t" } } */
       6  /* { dg-final { scan-assembler-not "ldwio\tr., %lo" } } */
       7  /* { dg-final { scan-assembler-not "stwio\tr., %lo" } } */
       8  
       9  /* Check that we do not generate %lo addresses with R2 ldstio instructions.
      10     %lo requires a 16-bit relocation and on R2 these instructions only have a
      11     12-bit register offset.  */
      12  
      13  #define TYPE int
      14  
      15  struct ss
      16  {
      17    TYPE x1,x2;
      18  };
      19  
      20  extern volatile TYPE S1;
      21  extern volatile TYPE S2[];
      22  
      23  extern volatile struct ss S3;
      24  extern volatile struct ss S4[];
      25  
      26  volatile TYPE *addr1 (void) { return &S1; }
      27  TYPE get1 (void) { return S1; }
      28  void set1 (TYPE value) { S1 = value; }
      29  
      30  volatile TYPE *addr2 (int i) { return &(S2[i]); }
      31  TYPE get2 (int i) { return S2[i]; }
      32  void set2 (int i, TYPE value) { S2[i] = value; }
      33  
      34  volatile TYPE *addr3 (void) { return &(S3.x2); }
      35  TYPE get3 (void) { return S3.x2; }
      36  void set3 (TYPE value) { S3.x2 = value; }
      37  
      38  volatile TYPE *addr4 (int i) { return &(S4[i].x2); }
      39  TYPE get4 (int i) { return S4[i].x2; }
      40  void set4 (int i, TYPE value) { S4[i].x2 = value; }
      41