1  /* { dg-do compile } */
       2  /* { dg-options "-O2 -march=r2 -mbypass-cache" } */
       3  /* { dg-final { scan-assembler-times "addi\tr., r., %lo" 12 } } */
       4  /* { dg-final { scan-assembler-not "ldw\t" } } */
       5  /* { dg-final { scan-assembler-not "stw\t" } } */
       6  /* { dg-final { scan-assembler-not "ldwio\tr., %lo" } } */
       7  /* { dg-final { scan-assembler-not "stwio\tr., %lo" } } */
       8  
       9  /* Check that we do not generate %lo addresses with R2 ldstio instructions.
      10     %lo requires a 16-bit relocation and on R2 these instructions only have a
      11     12-bit register offset.  */
      12  #define TYPE int
      13  
      14  struct ss
      15  {
      16    TYPE x1,x2;
      17  };
      18  
      19  extern TYPE S1;
      20  extern TYPE S2[];
      21  
      22  extern struct ss S3;
      23  extern struct ss S4[];
      24  
      25  TYPE *addr1 (void) { return &S1; }
      26  TYPE get1 (void) { return S1; }
      27  void set1 (TYPE value) { S1 = value; }
      28  
      29  TYPE *addr2 (int i) { return &(S2[i]); }
      30  TYPE get2 (int i) { return S2[i]; }
      31  void set2 (int i, TYPE value) { S2[i] = value; }
      32  
      33  TYPE *addr3 (void) { return &(S3.x2); }
      34  TYPE get3 (void) { return S3.x2; }
      35  void set3 (TYPE value) { S3.x2 = value; }
      36  
      37  TYPE *addr4 (int i) { return &(S4[i].x2); }
      38  TYPE get4 (int i) { return S4[i].x2; }
      39  void set4 (int i, TYPE value) { S4[i].x2 = value; }
      40