1  /* { dg-options "-mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */
       2  /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
       3  
       4  unsigned char *bar (int);
       5  
       6  /* Test that code after a branch-likely does not get an unnecessary
       7     cache barrier.  */
       8  
       9  NOMIPS16 void
      10  foo (unsigned char *n)
      11  {
      12    /* n starts in $4, but will be in $2 after the call to bar.
      13       Encourage it to be in $2 on entry to the loop as well,
      14       by doing some computation on it beforehand (D?ADDIU $2,$4,4).
      15       dbr_schedule should then pull the *n load (L[WD] ...,0($2))
      16       into the delay slot.  */
      17    n += 4;
      18    do
      19      n = bar (*n + 1);
      20    while (n);
      21    /* The preceding branch should be a branch likely, with the shift as
      22       its delay slot.  We therefore don't need a cache barrier here.  */
      23    n[0] = 0;
      24  }
      25  
      26  /* { dg-final { scan-assembler-not "\tcache\t" } } */