1 /* { dg-do run { target avx512fp16 } } */
2 /* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
3
4
5 #define AVX512FP16
6 #include "avx512fp16-helper.h"
7
8 #define N_ELEMS (AVX512F_LEN / 16)
9
10 void NOINLINE
11 EMULATE(cvtph2_d) (V512 * dest, V512 op1,
12 __mmask32 k, int zero_mask)
13 {
14 V512 v1, v2, v3, v4, v5, v6, v7, v8;
15 int i;
16 __mmask16 m1, m2;
17
18 m1 = k & 0xffff;
19
20 unpack_ph_2twops(op1, &v1, &v2);
21
22 for (i = 0; i < 16; i++) {
23 if (((1 << i) & m1) == 0) {
24 if (zero_mask) {
25 v5.u32[i] = 0;
26 }
27 else {
28 v5.u32[i] = dest->u32[i];
29 }
30 }
31 else {
32 v5.u32[i] = v1.f32[i];
33
34 }
35 }
36 *dest = v5;
37 }
38
39 void
40 TEST (void)
41 {
42 V512 res;
43 V512 exp;
44
45 init_src();
46
47 EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0);
48 SI(res) = INTRINSIC (_cvttph_epi32) (H_HF(src1));
49 CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi32);
50
51 init_dest(&res, &exp);
52 EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
53 SI(res) = INTRINSIC (_mask_cvttph_epi32) (SI(res), HALF_MASK, H_HF(src1));
54 CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi32);
55
56 EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1);
57 SI(res) = INTRINSIC (_maskz_cvttph_epi32) (HALF_MASK, H_HF(src1));
58 CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi32);
59
60 #if AVX512F_LEN == 512
61 EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0);
62 SI(res) = INTRINSIC (_cvtt_roundph_epi32) (H_HF(src1), _ROUND_NINT);
63 CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi32);
64
65 init_dest(&res, &exp);
66 EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
67 SI(res) = INTRINSIC (_mask_cvtt_roundph_epi32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT);
68 CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi32);
69
70 EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1);
71 SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi32) (HALF_MASK, H_HF(src1), _ROUND_NINT);
72 CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi32);
73 #endif
74
75 if (n_errs != 0)
76 abort ();
77 }
78
79