1  /* Ensure that explicit zero-entend instructions are present when compiling
       2     for targets without sram-ecc enabled (in which sub-dword loads do not
       3     zero the high bits of the target register).  */
       4  
       5  /* { dg-do compile } */
       6  /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=off" } */
       7  
       8  typedef unsigned int v64si __attribute__ ((vector_size (64*4)));
       9  typedef unsigned char v64qi __attribute__ ((vector_size (64*1)));
      10  
      11  extern v64si a;
      12  extern v64qi b;
      13  
      14  void
      15  f ()
      16  {
      17    for (int n = 0; n < 64; n++)
      18      a[n] = b[n];
      19  }
      20  
      21  /* { dg-final { scan-assembler "zero_extendv64qiv64si2" } } */