1  /* { dg-do compile } */
       2  /* { dg-require-effective-target arm_neon_ok } */
       3  /* { dg-add-options arm_neon } */
       4  /* { dg-additional-options "-O3" } */
       5  
       6  #include <stdint.h>
       7  
       8  /* Since we default to -mvectorize-with-neon-quad, use enough iterations so that
       9     we can vectorize using 128-bit vectors.  */
      10  /* We force a cast to int64_t to enable the vectorizer when dealing with 32-bit
      11     inputs.  */
      12  #define FUNC(SIGN, TYPE, BITS, OP, NAME)				\
      13    void test_ ## NAME ##_ ## SIGN ## BITS (TYPE##BITS##_t * __restrict__ dest, \
      14  					  TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
      15      int i;								\
      16      for (i=0; i < (128 / BITS); i++) {					\
      17        dest[i] = ((int64_t)a[i] OP b[i] + 1) >> 1;			\
      18      }									\
      19  }
      20  
      21  FUNC(s, int, 32, +, vrhadd)
      22  FUNC(u, uint, 32, +, vrhadd)
      23  FUNC(s, int, 16, +, vrhadd)
      24  FUNC(u, uint, 16, +, vrhadd)
      25  FUNC(s, int, 8, +, vrhadd)
      26  FUNC(u, uint, 8, +, vrhadd)
      27  
      28  /* { dg-final { scan-assembler-times {vrhadd\.s32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
      29  /* { dg-final { scan-assembler-times {vrhadd\.u32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
      30  /* { dg-final { scan-assembler-times {vrhadd\.s16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
      31  /* { dg-final { scan-assembler-times {vrhadd\.u16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
      32  /* { dg-final { scan-assembler-times {vrhadd\.s8\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
      33  /* { dg-final { scan-assembler-times {vrhadd\.u8\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */