1  /* { dg-do assemble } */
       2  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
       3  /* { dg-add-options arm_v8_1m_mve } */
       4  /* { dg-additional-options "-O3" } */
       5  
       6  /* Integer tests.  */
       7  
       8  #define COMPARE_REG(NAME, OP, TYPE) \
       9    TYPE \
      10    cmp_##NAME##_##TYPE##_reg (TYPE a, TYPE b) \
      11    { \
      12      return a OP b; \
      13    }
      14  
      15  #define COMPARE_REG_AND_ZERO(NAME, OP, TYPE) \
      16    COMPARE_REG (NAME, OP, TYPE) \
      17    \
      18    TYPE \
      19    cmp_##NAME##_##TYPE##_zero (TYPE a) \
      20    { \
      21      return a OP (TYPE) {}; \
      22    }
      23  
      24  #define COMPARE_TYPE(TYPE, COMPARE_ORDERED) \
      25    COMPARE_REG_AND_ZERO (eq, ==, TYPE) \
      26    COMPARE_REG_AND_ZERO (ne, !=, TYPE) \
      27    COMPARE_ORDERED (lt, <, TYPE) \
      28    COMPARE_ORDERED (le, <=, TYPE) \
      29    COMPARE_ORDERED (gt, >, TYPE) \
      30    COMPARE_ORDERED (ge, >=, TYPE)
      31  
      32  #define TEST_TYPE(NAME, ELEM, COMPARE_ORDERED, SIZE)  \
      33    typedef ELEM NAME##SIZE __attribute__((vector_size(SIZE))); \
      34    COMPARE_TYPE (NAME##SIZE, COMPARE_ORDERED)
      35  
      36  /* 64-bits vectors, not vectorized.  */
      37  TEST_TYPE (vs8, __INT8_TYPE__, COMPARE_REG_AND_ZERO, 8)
      38  TEST_TYPE (vu8, __UINT8_TYPE__, COMPARE_REG, 8)
      39  TEST_TYPE (vs16, __INT16_TYPE__, COMPARE_REG_AND_ZERO, 8)
      40  TEST_TYPE (vu16, __UINT16_TYPE__, COMPARE_REG, 8)
      41  TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO, 8)
      42  TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG, 8)
      43  
      44  /* 128-bits vectors.  */
      45  TEST_TYPE (vs8, __INT8_TYPE__, COMPARE_REG_AND_ZERO, 16)
      46  TEST_TYPE (vu8, __UINT8_TYPE__, COMPARE_REG, 16)
      47  TEST_TYPE (vs16, __INT16_TYPE__, COMPARE_REG_AND_ZERO, 16)
      48  TEST_TYPE (vu16, __UINT16_TYPE__, COMPARE_REG, 16)
      49  TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO, 16)
      50  TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG, 16)
      51  
      52  /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
      53  /* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 4 } } */
      54  /* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 4 } } */
      55  /* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
      56  /* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 2 } } */
      57  /* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
      58  /* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 2 } } */
      59  /* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */
      60  /* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
      61  
      62  /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
      63  /* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 4 } } */
      64  /* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 4 } } */
      65  /* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
      66  /* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 2 } } */
      67  /* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
      68  /* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 2 } } */
      69  /* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */
      70  /* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
      71  
      72  /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
      73  /* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 4 } } */
      74  /* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 4 } } */
      75  /* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
      76  /* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 2 } } */
      77  /* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
      78  /* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 2 } } */
      79  /* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */
      80  /* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */