1  /* { dg-do compile } */
       2  /* { dg-options "-O2" } */
       3  /* { dg-require-effective-target arm32 } */
       4  
       5  /* ARM has shift-and-alu insns.  Depending on the ALU op GCC represents some
       6     of these as a left shift, others as a multiply.  Check that we match the
       7      right one.  */
       8  
       9  int
      10  plus (int a, int b)
      11  {
      12    return (a * 64) + b;
      13  }
      14  
      15  /* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
      16  
      17  int
      18  minus (int a, int b)
      19  {
      20    return a - (b * 64);
      21  }
      22  
      23  /* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
      24  
      25  int
      26  ior (int a, int b)
      27  {
      28    return (a * 64) | b;
      29  }
      30  
      31  /* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
      32  
      33  int
      34  xor (int a, int b)
      35  {
      36    return (a * 64) ^ b;
      37  }
      38  
      39  /* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
      40  
      41  int
      42  and (int a, int b)
      43  {
      44    return (a * 64) & b;
      45  }
      46  
      47  /* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
      48  
      49  int
      50  rsb (int a, int b)
      51  {
      52    return (a * 64) - b;
      53  }
      54  
      55  /* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
      56  
      57  int
      58  mvn (int a, int b)
      59  {
      60    return ~(a * 64);
      61  }
      62  
      63  /* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */