1 /* { dg-do compile } */
2 /* { dg-require-effective-target arm_neon_ok } */
3 /* { dg-options "-O1" } */
4 /* { dg-add-options arm_neon } */
5
6 #define COMPARE_REG(NAME, OP, TYPE) \
7 TYPE \
8 cmp_##NAME##_##TYPE##_reg (TYPE a, TYPE b) \
9 { \
10 return a OP b; \
11 }
12
13 #define COMPARE_REG_AND_ZERO(NAME, OP, TYPE) \
14 COMPARE_REG (NAME, OP, TYPE) \
15 \
16 TYPE \
17 cmp_##NAME##_##TYPE##_zero (TYPE a) \
18 { \
19 return a OP (TYPE) {}; \
20 }
21
22 #define COMPARE_TYPE(TYPE, COMPARE_ORDERED) \
23 COMPARE_REG_AND_ZERO (eq, ==, TYPE) \
24 COMPARE_REG_AND_ZERO (ne, !=, TYPE) \
25 COMPARE_ORDERED (lt, <, TYPE) \
26 COMPARE_ORDERED (le, <=, TYPE) \
27 COMPARE_ORDERED (gt, >, TYPE) \
28 COMPARE_ORDERED (ge, >=, TYPE)
29
30 #define TEST_TYPE(NAME, ELEM, COMPARE_ORDERED) \
31 typedef ELEM NAME __attribute__((vector_size(16))); \
32 COMPARE_TYPE (NAME, COMPARE_ORDERED)
33
34 TEST_TYPE (vs8, __INT8_TYPE__, COMPARE_REG_AND_ZERO)
35 TEST_TYPE (vu8, __UINT8_TYPE__, COMPARE_REG)
36 TEST_TYPE (vs16, __INT16_TYPE__, COMPARE_REG_AND_ZERO)
37 TEST_TYPE (vu16, __UINT16_TYPE__, COMPARE_REG)
38 TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO)
39 TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG)
40
41 /* { s8, u8 } x { eq, ne }.
42 /* { dg-final { scan-assembler-times {\tvceq.i8\tq[0-9]+, q[0-9]+, q[0-9]+\n} 4 } } */
43 /* { dg-final { scan-assembler-times {\tvceq.i8\tq[0-9]+, q[0-9]+, #0\n} 4 } } */
44
45 /* { dg-final { scan-assembler-times {\tvcgt.s8\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
46 /* { dg-final { scan-assembler-times {\tvcgt.s8\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
47 /* { dg-final { scan-assembler-times {\tvclt.s8\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
48
49 /* { dg-final { scan-assembler-times {\tvcge.s8\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
50 /* { dg-final { scan-assembler-times {\tvcge.s8\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
51 /* { dg-final { scan-assembler-times {\tvcle.s8\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
52
53 /* { dg-final { scan-assembler-times {\tvcgt.u8\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
54 /* { dg-final { scan-assembler-times {\tvcge.u8\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
55
56 /* { s16, u16 } x { eq, ne }.
57 /* { dg-final { scan-assembler-times {\tvceq.i16\tq[0-9]+, q[0-9]+, q[0-9]+\n} 4 } } */
58 /* { dg-final { scan-assembler-times {\tvceq.i16\tq[0-9]+, q[0-9]+, #0\n} 4 } } */
59
60 /* { dg-final { scan-assembler-times {\tvcgt.s16\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
61 /* { dg-final { scan-assembler-times {\tvcgt.s16\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
62 /* { dg-final { scan-assembler-times {\tvclt.s16\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
63
64 /* { dg-final { scan-assembler-times {\tvcge.s16\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
65 /* { dg-final { scan-assembler-times {\tvcge.s16\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
66 /* { dg-final { scan-assembler-times {\tvcle.s16\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
67
68 /* { dg-final { scan-assembler-times {\tvcgt.u16\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
69 /* { dg-final { scan-assembler-times {\tvcge.u16\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
70
71 /* { s32, u32 } x { eq, ne }.
72 /* { dg-final { scan-assembler-times {\tvceq.i32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 4 } } */
73 /* { dg-final { scan-assembler-times {\tvceq.i32\tq[0-9]+, q[0-9]+, #0\n} 4 } } */
74
75 /* { dg-final { scan-assembler-times {\tvcgt.s32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
76 /* { dg-final { scan-assembler-times {\tvcgt.s32\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
77 /* { dg-final { scan-assembler-times {\tvclt.s32\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
78
79 /* { dg-final { scan-assembler-times {\tvcge.s32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
80 /* { dg-final { scan-assembler-times {\tvcge.s32\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
81 /* { dg-final { scan-assembler-times {\tvcle.s32\tq[0-9]+, q[0-9]+, #0\n} 1 } } */
82
83 /* { dg-final { scan-assembler-times {\tvcgt.u32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
84 /* { dg-final { scan-assembler-times {\tvcge.u32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */