1  /* Test the CDE ACLE intrinsic.  */
       2  /* { dg-do compile } */
       3  /* { dg-require-effective-target arm_v8_1m_main_cde_mve_ok } */
       4  /* { dg-options "-save-temps -O2" } */
       5  /* { dg-add-options arm_v8_1m_main_cde_mve } */
       6  
       7  #include "arm_cde.h"
       8  
       9  #define TEST0(T, N, C, I) \
      10  T test_arm_##N##_##C##_##I () { \
      11    return __arm_##N (C, I); \
      12  }
      13  
      14  #define TEST1(T, N, C, I) \
      15  T test_arm_##N##_##C##_##I (T a) { \
      16    return __arm_##N (C, a, I); \
      17  }
      18  
      19  #define TEST2(T, N, C, I) \
      20  T test_arm_##N##_##C##_##I (T a) { \
      21    return __arm_##N (C, a, a, I); \
      22  }
      23  
      24  #define TEST3(T, N, C, I) \
      25  T test_arm_##N##_##C##_##I (T a) { \
      26    return __arm_##N (C, a, a, a, I); \
      27  }
      28  
      29  #define TEST_ALL(C) \
      30  TEST0 (uint32_t, vcx1_u32,	C, 0) \
      31  TEST1 (uint32_t, vcx1a_u32,	C, 0) \
      32  TEST1 (uint32_t, vcx2_u32,	C, 0) \
      33  TEST2 (uint32_t, vcx2a_u32,	C, 0) \
      34  TEST2 (uint32_t, vcx3_u32,	C, 0) \
      35  TEST3 (uint32_t, vcx3a_u32,	C, 0) \
      36  TEST0 (uint64_t, vcx1d_u64,	C, 0) \
      37  TEST1 (uint64_t, vcx1da_u64,	C, 0) \
      38  TEST1 (uint64_t, vcx2d_u64,	C, 0) \
      39  TEST2 (uint64_t, vcx2da_u64,	C, 0) \
      40  TEST2 (uint64_t, vcx3d_u64,	C, 0) \
      41  TEST3 (uint64_t, vcx3da_u64,	C, 0)
      42  
      43  TEST_ALL (0)
      44  
      45  /* { dg-final { scan-assembler-times {\tvcx1\tp0, s[0-9]+, #0} 1 } } */
      46  /* { dg-final { scan-assembler-times {\tvcx1a\tp0, s[0-9]+, #0} 1 } } */
      47  /* { dg-final { scan-assembler-times {\tvcx2\tp0, s[0-9]+, s[0-9]+, #0} 1 } } */
      48  /* { dg-final { scan-assembler-times {\tvcx2a\tp0, s[0-9]+, s[0-9]+, #0} 1 } } */
      49  /* { dg-final { scan-assembler-times {\tvcx3\tp0, s[0-9]+, s[0-9]+, s[0-9]+, #0} 1 } } */
      50  /* { dg-final { scan-assembler-times {\tvcx3a\tp0, s[0-9]+, s[0-9]+, s[0-9]+, #0} 1 } } */
      51  /* { dg-final { scan-assembler-times {\tvcx1\tp0, d[0-9]+, #0} 1 } } */
      52  /* { dg-final { scan-assembler-times {\tvcx1a\tp0, d[0-9]+, #0} 1 } } */
      53  /* { dg-final { scan-assembler-times {\tvcx2\tp0, d[0-9]+, d[0-9]+, #0} 1 } } */
      54  /* { dg-final { scan-assembler-times {\tvcx2a\tp0, d[0-9]+, d[0-9]+, #0} 1 } } */
      55  /* { dg-final { scan-assembler-times {\tvcx3\tp0, d[0-9]+, d[0-9]+, d[0-9]+, #0} 1 } } */
      56  /* { dg-final { scan-assembler-times {\tvcx3a\tp0, d[0-9]+, d[0-9]+, d[0-9]+, #0} 1 } } */