1 /* Test the CDE ACLE intrinsic. */
2 /* { dg-do compile } */
3 /* { dg-require-effective-target arm_v8m_main_cde_fp_ok } */
4 /* { dg-options "-save-temps -O2" } */
5 /* { dg-add-options arm_v8m_main_cde_fp } */
6
7 #include "arm_cde.h"
8
9 #define TEST0(T, N, C, I) \
10 T test_arm_##N##_##C##_##I () { \
11 return __arm_##N (C, I); \
12 }
13
14 #define TEST1(T, N, C, I) \
15 T test_arm_##N##_##C##_##I (T a) { \
16 return __arm_##N (C, a, I); \
17 }
18
19 #define TEST2(T, N, C, I) \
20 T test_arm_##N##_##C##_##I (T a) { \
21 return __arm_##N (C, a, a, I); \
22 }
23
24 #define TEST3(T, N, C, I) \
25 T test_arm_##N##_##C##_##I (T a) { \
26 return __arm_##N (C, a, a, a, I); \
27 }
28
29 #define TEST_ALL(C) \
30 TEST0 (uint32_t, vcx1_u32, C, 0) \
31 TEST1 (uint32_t, vcx1a_u32, C, 0) \
32 TEST1 (uint32_t, vcx2_u32, C, 0) \
33 TEST2 (uint32_t, vcx2a_u32, C, 0) \
34 TEST2 (uint32_t, vcx3_u32, C, 0) \
35 TEST3 (uint32_t, vcx3a_u32, C, 0) \
36 TEST0 (uint64_t, vcx1d_u64, C, 0) \
37 TEST1 (uint64_t, vcx1da_u64, C, 0) \
38 TEST1 (uint64_t, vcx2d_u64, C, 0) \
39 TEST2 (uint64_t, vcx2da_u64, C, 0) \
40 TEST2 (uint64_t, vcx3d_u64, C, 0) \
41 TEST3 (uint64_t, vcx3da_u64, C, 0) \
42 TEST0 (uint32_t, vcx1_u32, C, 2047) \
43 TEST1 (uint32_t, vcx1a_u32, C, 2047) \
44 TEST1 (uint32_t, vcx2_u32, C, 63) \
45 TEST2 (uint32_t, vcx2a_u32, C, 63) \
46 TEST2 (uint32_t, vcx3_u32, C, 7) \
47 TEST3 (uint32_t, vcx3a_u32, C, 7) \
48 TEST0 (uint64_t, vcx1d_u64, C, 2047) \
49 TEST1 (uint64_t, vcx1da_u64, C, 2047) \
50 TEST1 (uint64_t, vcx2d_u64, C, 63) \
51 TEST2 (uint64_t, vcx2da_u64, C, 63) \
52 TEST2 (uint64_t, vcx3d_u64, C, 7) \
53 TEST3 (uint64_t, vcx3da_u64, C, 7)
54
55 #pragma GCC push_options
56 #pragma GCC target ("arch=armv8-m.main+cdecp0+fp")
57 TEST_ALL (0)
58 #pragma GCC pop_options
59
60 #pragma GCC push_options
61 #pragma GCC target ("arch=armv8-m.main+cdecp1+fp")
62 TEST_ALL (1)
63 #pragma GCC pop_options
64
65 #pragma GCC push_options
66 #pragma GCC target ("arch=armv8-m.main+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp")
67 TEST_ALL (2)
68 TEST_ALL (3)
69 TEST_ALL (4)
70 TEST_ALL (5)
71 TEST_ALL (6)
72 TEST_ALL (7)
73 #pragma GCC pop_options
74
75 /* { dg-final { scan-assembler-times {\tvcx1\tp0, s[0-9]+, #0} 1 } } */
76 /* { dg-final { scan-assembler-times {\tvcx1\tp1, s[0-9]+, #0} 1 } } */
77 /* { dg-final { scan-assembler-times {\tvcx1\tp2, s[0-9]+, #0} 1 } } */
78 /* { dg-final { scan-assembler-times {\tvcx1\tp3, s[0-9]+, #0} 1 } } */
79 /* { dg-final { scan-assembler-times {\tvcx1\tp4, s[0-9]+, #0} 1 } } */
80 /* { dg-final { scan-assembler-times {\tvcx1\tp5, s[0-9]+, #0} 1 } } */
81 /* { dg-final { scan-assembler-times {\tvcx1\tp6, s[0-9]+, #0} 1 } } */
82 /* { dg-final { scan-assembler-times {\tvcx1\tp7, s[0-9]+, #0} 1 } } */
83 /* { dg-final { scan-assembler-times {\tvcx1\tp[0-7], s[0-9]+, #2047} 8 } } */
84 /* { dg-final { scan-assembler-times {\tvcx1a\tp[0-7], s[0-9]+, #[0,2047]} 16 } } */
85 /* { dg-final { scan-assembler-times {\tvcx2\tp[0-7], s[0-9]+, s[0-9]+, #[0,63]} 16 } } */
86 /* { dg-final { scan-assembler-times {\tvcx2a\tp[0-7], s[0-9]+, s[0-9]+, #[0,63]} 16 } } */
87 /* { dg-final { scan-assembler-times {\tvcx3\tp[0-7], s[0-9]+, s[0-9]+, s[0-9]+, #[0,7]} 16 } } */
88 /* { dg-final { scan-assembler-times {\tvcx3a\tp[0-7], s[0-9]+, s[0-9]+, s[0-9]+, #[0,7]} 16 } } */
89 /* { dg-final { scan-assembler-times {\tvcx1\tp[0-7], d[0-9]+, #[0,2047]} 16 } } */
90 /* { dg-final { scan-assembler-times {\tvcx1a\tp[0-7], d[0-9]+, #[0,2047]} 16 } } */
91 /* { dg-final { scan-assembler-times {\tvcx2\tp[0-7], d[0-9]+, d[0-9]+, #[0,63]} 16 } } */
92 /* { dg-final { scan-assembler-times {\tvcx2a\tp[0-7], d[0-9]+, d[0-9]+, #[0,63]} 16 } } */
93 /* { dg-final { scan-assembler-times {\tvcx3\tp[0-7], d[0-9]+, d[0-9]+, d[0-9]+, #[0,7]} 16 } } */
94 /* { dg-final { scan-assembler-times {\tvcx3a\tp[0-7], d[0-9]+, d[0-9]+, d[0-9]+, #[0,7]} 16 } } */