1  /* { dg-do compile } */
       2  /* { dg-options "-O -msve-vector-bits=256" } */
       3  
       4  #include <stdint.h>
       5  
       6  typedef int64_t vnx2di __attribute__((vector_size (32)));
       7  typedef int32_t vnx4si __attribute__((vector_size (32)));
       8  typedef int16_t vnx8hi __attribute__((vector_size (32)));
       9  typedef int8_t vnx16qi __attribute__((vector_size (32)));
      10  typedef double vnx2df __attribute__((vector_size (32)));
      11  typedef float vnx4sf __attribute__((vector_size (32)));
      12  typedef _Float16 vnx8hf __attribute__((vector_size (32)));
      13  
      14  #define VEC_PERM(TYPE, MASKTYPE)			\
      15  TYPE vec_perm_##TYPE (TYPE values, MASKTYPE mask)	\
      16  {							\
      17    return __builtin_shuffle (values, mask);		\
      18  }
      19  
      20  VEC_PERM (vnx2di, vnx2di)
      21  VEC_PERM (vnx4si, vnx4si)
      22  VEC_PERM (vnx8hi, vnx8hi)
      23  VEC_PERM (vnx16qi, vnx16qi)
      24  VEC_PERM (vnx2df, vnx2di)
      25  VEC_PERM (vnx4sf, vnx4si)
      26  VEC_PERM (vnx8hf, vnx8hi)
      27  
      28  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
      29  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
      30  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
      31  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */