(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
aarch64/
sve/
vec_perm_const_1.c
       1  /* { dg-do compile } */
       2  /* { dg-options "-O -msve-vector-bits=256" } */
       3  
       4  #include <stdint.h>
       5  
       6  typedef int64_t vnx2di __attribute__((vector_size (32)));
       7  typedef int32_t vnx4si __attribute__((vector_size (32)));
       8  typedef int16_t vnx8hi __attribute__((vector_size (32)));
       9  typedef int8_t vnx16qi __attribute__((vector_size (32)));
      10  typedef double vnx2df __attribute__((vector_size (32)));
      11  typedef float vnx4sf __attribute__((vector_size (32)));
      12  typedef _Float16 vnx8hf __attribute__((vector_size (32)));
      13  
      14  #define VEC_PERM_CONST(TYPE, MASK)			\
      15  TYPE __attribute__ ((noinline, noclone)) 		\
      16  vec_perm_##TYPE (TYPE values1, TYPE values2)		\
      17  {							\
      18    return __builtin_shuffle (values1, values2, MASK);	\
      19  }
      20  
      21  VEC_PERM_CONST (vnx2di,  ((vnx2di)  { 4, 3, 6, 1 }));
      22  VEC_PERM_CONST (vnx4si,  ((vnx4si)  { 3, 9, 11, 12, 2, 4, 4, 2 }));
      23  VEC_PERM_CONST (vnx8hi,  ((vnx8hi)  { 8, 27, 5, 4, 21, 12, 13, 0,
      24  				      22, 1, 8, 9, 3, 24, 15, 1 }));
      25  VEC_PERM_CONST (vnx16qi, ((vnx16qi) { 13, 31, 11, 2, 48, 28, 3, 4,
      26  				      54, 11, 30, 1, 0, 61, 2, 3,
      27  				      4, 5, 11, 63, 24, 11, 42, 39,
      28  				      2, 57, 22, 11, 6, 16, 18, 21 }));
      29  VEC_PERM_CONST (vnx2df,  ((vnx2di) { 7, 3, 2, 1 }));
      30  VEC_PERM_CONST (vnx4sf,  ((vnx4si) { 1, 9, 13, 11, 2, 5, 4, 2 }));
      31  VEC_PERM_CONST (vnx8hf,  ((vnx8hi) { 8, 27, 5, 4, 21, 12, 13, 0,
      32  				     22, 1, 8, 9, 3, 24, 15, 1 }));
      33  
      34  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */
      35  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */
      36  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */
      37  /* { dg-final { scan-assembler-times {\ttbl\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */