1 /* { dg-do run { target aarch64_sve_hw } } */
2 /* { dg-options "-O" } */
3 /* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
4
5 #include "vec_perm_1.c"
6
7 #define TEST_VEC_PERM(TYPE, MASK_TYPE, EXPECTED_RESULT, \
8 VALUES1, VALUES2, MASK) \
9 { \
10 TYPE expected_result = EXPECTED_RESULT; \
11 TYPE values1 = VALUES1; \
12 TYPE values2 = VALUES2; \
13 MASK_TYPE mask = MASK; \
14 TYPE dest; \
15 dest = vec_perm_##TYPE (values1, values2, mask); \
16 if (__builtin_memcmp (&dest, &expected_result, sizeof (TYPE)) != 0) \
17 __builtin_abort (); \
18 }
19
20 int main (void)
21 {
22 TEST_VEC_PERM (vnx2di, vnx2di,
23 ((vnx2di) { 5, 36, 7, 48 }),
24 ((vnx2di) { 4, 5, 6, 7 }),
25 ((vnx2di) { 12, 24, 36, 48 }),
26 ((vnx2di) { 1 + (8 * 1), 6 + (8 * 3),
27 3 + (8 * 1), 7 + (8 * 5) }));
28 TEST_VEC_PERM (vnx4si, vnx4si,
29 ((vnx4si) { 34, 38, 40, 10, 9, 8, 7, 35 }),
30 ((vnx4si) { 3, 4, 5, 6, 7, 8, 9, 10 }),
31 ((vnx4si) { 33, 34, 35, 36, 37, 38, 39, 40 }),
32 ((vnx4si) { 9 + (16 * 2), 13 + (16 * 5),
33 15 + (16 * 1), 7 + (16 * 0),
34 6 + (16 * 8), 5 + (16 * 2),
35 4 + (16 * 3), 10 + (16 * 2) }));
36 TEST_VEC_PERM (vnx8hi, vnx8hi,
37 ((vnx8hi) { 12, 16, 18, 10, 42, 43, 44, 34,
38 7, 48, 3, 35, 9, 8, 7, 13 }),
39 ((vnx8hi) { 3, 4, 5, 6, 7, 8, 9, 10,
40 11, 12, 13, 14, 15, 16, 17, 18 }),
41 ((vnx8hi) { 33, 34, 35, 36, 37, 38, 39, 40,
42 41, 42, 43, 44, 45, 46, 47, 48 }),
43 ((vnx8hi) { 9 + (32 * 2), 13 + (32 * 2),
44 15 + (32 * 8), 7 + (32 * 9),
45 25 + (32 * 4), 26 + (32 * 3),
46 27 + (32 * 1), 17 + (32 * 2),
47 4 + (32 * 6), 31 + (32 * 7),
48 0 + (32 * 8), 18 + (32 * 9),
49 6 + (32 * 6), 5 + (32 * 7),
50 4 + (32 * 2), 10 + (32 * 2) }));
51 TEST_VEC_PERM (vnx16qi, vnx16qi,
52 ((vnx16qi) { 5, 6, 7, 4, 5, 6, 4, 5,
53 6, 7, 12, 24, 36, 48, 12, 24,
54 5, 6, 7, 4, 5, 6, 4, 5,
55 6, 7, 12, 24, 36, 48, 12, 24 }),
56 ((vnx16qi) { 4, 5, 6, 7, 4, 5, 6, 7,
57 4, 5, 6, 7, 4, 5, 6, 7,
58 4, 5, 6, 7, 4, 5, 6, 7,
59 4, 5, 6, 7, 4, 5, 6, 7 }),
60 ((vnx16qi) { 12, 24, 36, 48, 12, 24, 36, 48,
61 12, 24, 36, 48, 12, 24, 36, 48,
62 12, 24, 36, 48, 12, 24, 36, 48,
63 12, 24, 36, 48, 12, 24, 36, 48 }),
64 ((vnx16qi) { 5 + (64 * 3), 6 + (64 * 1),
65 7 + (64 * 2), 8 + (64 * 1),
66 9 + (64 * 3), 10 + (64 * 1),
67 28 + (64 * 3), 29 + (64 * 3),
68 30 + (64 * 1), 31 + (64 * 1),
69 32 + (64 * 3), 33 + (64 * 2),
70 54 + (64 * 2), 55 + (64 * 2),
71 56 + (64 * 1), 61 + (64 * 2),
72 5 + (64 * 2), 6 + (64 * 1),
73 7 + (64 * 2), 8 + (64 * 2),
74 9 + (64 * 2), 10 + (64 * 1),
75 28 + (64 * 3), 29 + (64 * 1),
76 30 + (64 * 3), 31 + (64 * 3),
77 32 + (64 * 1), 33 + (64 * 1),
78 54 + (64 * 2), 55 + (64 * 2),
79 56 + (64 * 2), 61 + (64 * 2) }));
80 TEST_VEC_PERM (vnx2df, vnx2di,
81 ((vnx2df) { 5.1, 36.1, 7.1, 48.1 }),
82 ((vnx2df) { 4.1, 5.1, 6.1, 7.1 }),
83 ((vnx2df) { 12.1, 24.1, 36.1, 48.1 }),
84 ((vnx2di) { 1 + (8 * 3), 6 + (8 * 10),
85 3 + (8 * 8), 7 + (8 * 2) }));
86 TEST_VEC_PERM (vnx4sf, vnx4si,
87 ((vnx4sf) { 34.2, 38.2, 40.2, 10.2, 9.2, 8.2, 7.2, 35.2 }),
88 ((vnx4sf) { 3.2, 4.2, 5.2, 6.2, 7.2, 8.2, 9.2, 10.2 }),
89 ((vnx4sf) { 33.2, 34.2, 35.2, 36.2,
90 37.2, 38.2, 39.2, 40.2 }),
91 ((vnx4si) { 9 + (16 * 1), 13 + (16 * 5),
92 15 + (16 * 4), 7 + (16 * 4),
93 6 + (16 * 3), 5 + (16 * 2),
94 4 + (16 * 1), 10 + (16 * 0) }));
95 TEST_VEC_PERM (vnx8hf, vnx8hi,
96 ((vnx8hf) { 12.0, 16.0, 18.0, 10.0, 42.0, 43.0, 44.0, 34.0,
97 7.0, 48.0, 3.0, 35.0, 9.0, 8.0, 7.0, 13.0 }),
98 ((vnx8hf) { 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0,
99 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0 }),
100 ((vnx8hf) { 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0,
101 41.0, 42.0, 43.0, 44.0, 45.0, 46.0, 47.0, 48.0 }),
102 ((vnx8hi) { 9 + (32 * 2), 13 + (32 * 2),
103 15 + (32 * 8), 7 + (32 * 9),
104 25 + (32 * 4), 26 + (32 * 3),
105 27 + (32 * 1), 17 + (32 * 2),
106 4 + (32 * 6), 31 + (32 * 7),
107 0 + (32 * 8), 18 + (32 * 9),
108 6 + (32 * 6), 5 + (32 * 7),
109 4 + (32 * 2), 10 + (32 * 2) }));
110 return 0;
111 }