1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
2 /* { dg-options "-O -msve-vector-bits=256 -mlittle-endian --save-temps" } */
3
4 typedef char vnx16qi __attribute__((vector_size(32)));
5 typedef struct { vnx16qi a[2]; } vnx32qi;
6
7 typedef short vnx8hi __attribute__((vector_size(32)));
8 typedef struct { vnx8hi a[2]; } vnx16hi;
9
10 typedef int vnx4si __attribute__((vector_size(32)));
11 typedef struct { vnx4si a[2]; } vnx8si;
12
13 typedef long vnx2di __attribute__((vector_size(32)));
14 typedef struct { vnx2di a[2]; } vnx4di;
15
16 typedef float vnx4sf __attribute__((vector_size(32)));
17 typedef struct { vnx4sf a[2]; } vnx8sf;
18
19 typedef double vnx2df __attribute__((vector_size(32)));
20 typedef struct { vnx2df a[2]; } vnx4df;
21
22 #define TEST_TYPE(TYPE, REG1, REG2) \
23 void \
24 f1_##TYPE (TYPE *a) \
25 { \
26 register TYPE x asm (#REG1) = a[0]; \
27 asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \
28 register TYPE y asm (#REG2) = x; \
29 asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \
30 : "=&w" (x) : "0" (x), "w" (y)); \
31 a[1] = x; \
32 } \
33 /* This must compile, but we don't care how. */ \
34 void \
35 f2_##TYPE (TYPE *a) \
36 { \
37 TYPE x = a[0]; \
38 x.a[0][3] = 1; \
39 x.a[1][2] = 12; \
40 asm volatile ("# %0" :: "w" (x)); \
41 } \
42 void \
43 f3_##TYPE (TYPE *a, int i) \
44 { \
45 TYPE x = a[0]; \
46 x.a[0][i] = 1; \
47 asm volatile ("# %0" :: "w" (x)); \
48 } \
49 void \
50 f4_##TYPE (TYPE *a, int i, int j) \
51 { \
52 TYPE x = a[0]; \
53 x.a[i][j] = 44; \
54 asm volatile ("# %0" :: "w" (x)); \
55 }
56
57 TEST_TYPE (vnx32qi, z0, z2)
58 TEST_TYPE (vnx16hi, z5, z7)
59 TEST_TYPE (vnx8si, z10, z12)
60 TEST_TYPE (vnx4di, z15, z17)
61 TEST_TYPE (vnx8sf, z20, z23)
62 TEST_TYPE (vnx4df, z28, z30)
63
64 /* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */
65 /* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */
66 /* { dg-final { scan-assembler { test vnx32qi 1 z0\n} } } */
67 /* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */
68 /* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */
69 /* { dg-final { scan-assembler { test vnx32qi 2 z0, z0, z2\n} } } */
70 /* { dg-final { scan-assembler {\tstr\tz0, \[x0, #2, mul vl\]\n} } } */
71 /* { dg-final { scan-assembler {\tstr\tz1, \[x0, #3, mul vl\]\n} } } */
72
73 /* { dg-final { scan-assembler {\tldr\tz5, \[x0\]\n} } } */
74 /* { dg-final { scan-assembler {\tldr\tz6, \[x0, #1, mul vl\]\n} } } */
75 /* { dg-final { scan-assembler { test vnx16hi 1 z5\n} } } */
76 /* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */
77 /* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */
78 /* { dg-final { scan-assembler { test vnx16hi 2 z5, z5, z7\n} } } */
79 /* { dg-final { scan-assembler {\tstr\tz5, \[x0, #2, mul vl\]\n} } } */
80 /* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */
81
82 /* { dg-final { scan-assembler {\tldr\tz10, \[x0\]\n} } } */
83 /* { dg-final { scan-assembler {\tldr\tz11, \[x0, #1, mul vl\]\n} } } */
84 /* { dg-final { scan-assembler { test vnx8si 1 z10\n} } } */
85 /* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */
86 /* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */
87 /* { dg-final { scan-assembler { test vnx8si 2 z10, z10, z12\n} } } */
88 /* { dg-final { scan-assembler {\tstr\tz10, \[x0, #2, mul vl\]\n} } } */
89 /* { dg-final { scan-assembler {\tstr\tz11, \[x0, #3, mul vl\]\n} } } */
90
91 /* { dg-final { scan-assembler {\tldr\tz15, \[x0\]\n} } } */
92 /* { dg-final { scan-assembler {\tldr\tz16, \[x0, #1, mul vl\]\n} } } */
93 /* { dg-final { scan-assembler { test vnx4di 1 z15\n} } } */
94 /* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */
95 /* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */
96 /* { dg-final { scan-assembler { test vnx4di 2 z15, z15, z17\n} } } */
97 /* { dg-final { scan-assembler {\tstr\tz15, \[x0, #2, mul vl\]\n} } } */
98 /* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */
99
100 /* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */
101 /* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */
102 /* { dg-final { scan-assembler { test vnx8sf 1 z20\n} } } */
103 /* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */
104 /* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */
105 /* { dg-final { scan-assembler { test vnx8sf 2 z20, z20, z23\n} } } */
106 /* { dg-final { scan-assembler {\tstr\tz20, \[x0, #2, mul vl\]\n} } } */
107 /* { dg-final { scan-assembler {\tstr\tz21, \[x0, #3, mul vl\]\n} } } */
108
109 /* { dg-final { scan-assembler {\tldr\tz28, \[x0\]\n} } } */
110 /* { dg-final { scan-assembler {\tldr\tz29, \[x0, #1, mul vl\]\n} } } */
111 /* { dg-final { scan-assembler { test vnx4df 1 z28\n} } } */
112 /* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */
113 /* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */
114 /* { dg-final { scan-assembler { test vnx4df 2 z28, z28, z30\n} } } */
115 /* { dg-final { scan-assembler {\tstr\tz28, \[x0, #2, mul vl\]\n} } } */
116 /* { dg-final { scan-assembler {\tstr\tz29, \[x0, #3, mul vl\]\n} } } */