1  /* { dg-do run { target aarch64_sve_hw } } */
       2  /* { dg-options "-O2 -ftree-vectorize" } */
       3  
       4  #include "slp_10.c"
       5  
       6  #define N1 (103 * 2)
       7  #define N2 (111 * 2)
       8  
       9  #define HARNESS(TYPE)						\
      10    {								\
      11      TYPE a[N2], b[N2 * 4];					\
      12      for (unsigned int i = 0; i < N2; ++i)			\
      13        {								\
      14  	a[i] = i * 2 + i % 5;					\
      15  	b[i * 4] = i * 3 + i % 7;				\
      16  	b[i * 4 + 1] = i * 5 + i % 9;				\
      17  	b[i * 4 + 2] = i * 7 + i % 11;				\
      18  	b[i * 4 + 3] = i * 9 + i % 13;				\
      19        }								\
      20      vec_slp_##TYPE (a, b, N1);					\
      21      for (unsigned int i = 0; i < N2; ++i)			\
      22        {								\
      23  	TYPE orig_a = i * 2 + i % 5;				\
      24  	TYPE orig_b1 = i * 3 + i % 7;				\
      25  	TYPE orig_b2 = i * 5 + i % 9;				\
      26  	TYPE orig_b3 = i * 7 + i % 11;				\
      27  	TYPE orig_b4 = i * 9 + i % 13;				\
      28  	TYPE expected_a = orig_a;				\
      29  	TYPE expected_b1 = orig_b1;				\
      30  	TYPE expected_b2 = orig_b2;				\
      31  	TYPE expected_b3 = orig_b3;				\
      32  	TYPE expected_b4 = orig_b4;				\
      33  	if (i < N1)						\
      34  	  {							\
      35  	    expected_a += 1;					\
      36  	    expected_b1 += 2;					\
      37  	    expected_b2 += 3;					\
      38  	    expected_b3 += 4;					\
      39  	    expected_b4 += 5;					\
      40  	  }							\
      41  	if (a[i] != expected_a					\
      42  	    || b[i * 4] != expected_b1				\
      43  	    || b[i * 4 + 1] != expected_b2			\
      44  	    || b[i * 4 + 2] != expected_b3			\
      45  	    || b[i * 4 + 3] != expected_b4)			\
      46  	  __builtin_abort ();					\
      47        }								\
      48    }
      49  
      50  int __attribute__ ((optimize (1)))
      51  main (void)
      52  {
      53    TEST_ALL (HARNESS)
      54  }