1  /* { dg-do assemble { target aarch64_asm_sve_ok } } */
       2  /* { dg-options "-O -msve-vector-bits=2048 -mbig-endian --save-temps" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  typedef unsigned char v128qi __attribute__((vector_size(128)));
       6  typedef unsigned char v64qi __attribute__((vector_size(64)));
       7  typedef unsigned short v64hi __attribute__((vector_size(128)));
       8  typedef _Float16 v64hf __attribute__((vector_size(128)));
       9  typedef __bf16 v64bf __attribute__((vector_size(128)));
      10  
      11  #define PERM0(B) B + 1, B
      12  #define PERM1(B) PERM0 (B), PERM0 (B + 2)
      13  #define PERM2(B) PERM1 (B), PERM1 (B + 4)
      14  #define PERM3(B) PERM2 (B), PERM2 (B + 8)
      15  #define PERM4(B) PERM3 (B), PERM3 (B + 16)
      16  #define PERM5(B) PERM4 (B), PERM4 (B + 32)
      17  #define PERM6(B) PERM5 (B), PERM5 (B + 64)
      18  
      19  /*
      20  ** qi_revh_s:
      21  **	ptrue	(p[0-7])\.b, vl256
      22  **	ld1b	(z[0-9]+)\.h, \1/z, \[x0\]
      23  **	revh	(z[0-9]+)\.s, \1/m, \2\.s
      24  **	st1b	\3\.h, \1, \[x8\]
      25  **	ret
      26  */
      27  v128qi
      28  qi_revh_s (v128qi x)
      29  {
      30    return __builtin_shuffle (x, x, (v128qi) { PERM6 (0) });
      31  }
      32  
      33  /*
      34  ** qi_revw_d:
      35  **	ptrue	(p[0-7])\.b, vl256
      36  **	ld1b	(z[0-9]+)\.s, \1/z, \[x0\]
      37  **	revw	(z[0-9]+)\.d, \1/m, \2\.d
      38  **	st1b	\3\.s, \1, \[x8\]
      39  **	ret
      40  */
      41  v64qi
      42  qi_revw_d (v64qi x)
      43  {
      44    return __builtin_shuffle (x, x, (v64qi) { PERM5 (0) });
      45  }
      46  
      47  /*
      48  ** hi_revw_d:
      49  **	ptrue	(p[0-7])\.b, vl256
      50  **	ld1h	(z[0-9]+)\.s, \1/z, \[x0\]
      51  **	revw	(z[0-9]+)\.d, \1/m, \2\.d
      52  **	st1h	\3\.s, \1, \[x8\]
      53  **	ret
      54  */
      55  v64hi
      56  hi_revw_d (v64hi x)
      57  {
      58    return __builtin_shuffle (x, x, (v64hi) { PERM5 (0) });
      59  }
      60  
      61  /*
      62  ** hf_revw_d:
      63  **	ptrue	(p[0-7])\.b, vl256
      64  **	ld1h	(z[0-9]+)\.s, \1/z, \[x0\]
      65  **	revw	(z[0-9]+)\.d, \1/m, \2\.d
      66  **	st1h	\3\.s, \1, \[x8\]
      67  **	ret
      68  */
      69  v64hf
      70  hf_revw_d (v64hf x)
      71  {
      72    return __builtin_shuffle (x, x, (v64hi) { PERM5 (0) });
      73  }
      74  
      75  /*
      76  ** bf_revw_d:
      77  **	ptrue	(p[0-7])\.b, vl256
      78  **	ld1h	(z[0-9]+)\.s, \1/z, \[x0\]
      79  **	revw	(z[0-9]+)\.d, \1/m, \2\.d
      80  **	st1h	\3\.s, \1, \[x8\]
      81  **	ret
      82  */
      83  v64bf
      84  bf_revw_d (v64bf x)
      85  {
      86    return __builtin_shuffle (x, x, (v64hi) { PERM5 (0) });
      87  }
      88  
      89  #undef PERM1
      90  #define PERM1(B) PERM0 (B + 2), PERM0 (B)
      91  
      92  /*
      93  ** qi_revh_d:
      94  **	ptrue	(p[0-7])\.b, vl256
      95  **	ld1b	(z[0-9]+)\.h, \1/z, \[x0\]
      96  **	revh	(z[0-9]+)\.d, \1/m, \2\.d
      97  **	st1b	\3\.h, \1, \[x8\]
      98  **	ret
      99  */
     100  v128qi
     101  qi_revh_d (v128qi x)
     102  {
     103    return __builtin_shuffle (x, x, (v128qi) { PERM6 (0) });
     104  }
     105  
     106  v64qi
     107  qi_revw_q (v64qi x)
     108  {
     109    return __builtin_shuffle (x, x, (v64qi) { PERM5 (0) });
     110  }
     111  
     112  v64hi
     113  hi_revw_q (v64hi x)
     114  {
     115    return __builtin_shuffle (x, x, (v64hi) { PERM5 (0) });
     116  }
     117  
     118  #undef PERM2
     119  #define PERM2(B) PERM0 (B + 4), PERM0 (B)
     120  
     121  v128qi
     122  qi_revh_q (v128qi x)
     123  {
     124    return __builtin_shuffle (x, x, (v128qi) { PERM6 (0) });
     125  }
     126  
     127  /* { dg-final { scan-assembler-times {\trev.\t} 6 } } */