1  /* { dg-do assemble { target aarch64_asm_sve_ok } } */
       2  /* { dg-options "-O -msve-vector-bits=256 --save-temps -mlittle-endian" } */
       3  
       4  typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size (32)));
       5  
       6  #define MASK_2(X, Y) (X) ^ (Y), (X + 1) ^ (Y)
       7  #define MASK_4(X, Y) MASK_2 (X, Y), MASK_2 (X + 2, Y)
       8  #define MASK_8(X, Y) MASK_4 (X, Y), MASK_4 (X + 4, Y)
       9  #define MASK_16(X, Y) MASK_8 (X, Y), MASK_8 (X + 8, Y)
      10  #define MASK_32(X, Y) MASK_16 (X, Y), MASK_16 (X + 16, Y)
      11  
      12  #define INDEX_32 vnx16qi
      13  
      14  #define PERMUTE(TYPE, NUNITS, REV_NUNITS)				\
      15    TYPE permute_##TYPE##_##REV_NUNITS (TYPE values1, TYPE values2)	\
      16    {									\
      17      return __builtin_shuffle						\
      18        (values1, values2,						\
      19         ((INDEX_##NUNITS) { MASK_##NUNITS (0, REV_NUNITS - 1) }));	\
      20    }
      21  
      22  #define TEST_ALL(T)				\
      23    T (vnx16qi, 32, 2)				\
      24    T (vnx16qi, 32, 4)				\
      25    T (vnx16qi, 32, 8)
      26  
      27  TEST_ALL (PERMUTE)
      28  
      29  /* { dg-final { scan-assembler-not {\ttbl\t} } } */
      30  
      31  /* { dg-final { scan-assembler-times {\trevb\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d} 1 } } */
      32  /* { dg-final { scan-assembler-times {\trevb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s} 1 } } */
      33  /* { dg-final { scan-assembler-times {\trevb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h} 1 } } */