1 /* { dg-do compile } */
2 /* { dg-options "-O -mlittle-endian -fshrink-wrap -fstack-clash-protection -msve-vector-bits=2048 -g" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4
5 #pragma GCC aarch64 "arm_sve.h"
6
7 /*
8 ** test_1:
9 ** mov x12, #?4608
10 ** sub sp, sp, x12
11 ** str p4, \[sp\]
12 ** str p5, \[sp, #1, mul vl\]
13 ** str p6, \[sp, #2, mul vl\]
14 ** str p7, \[sp, #3, mul vl\]
15 ** str p8, \[sp, #4, mul vl\]
16 ** str p9, \[sp, #5, mul vl\]
17 ** str p10, \[sp, #6, mul vl\]
18 ** str p11, \[sp, #7, mul vl\]
19 ** str p12, \[sp, #8, mul vl\]
20 ** str p13, \[sp, #9, mul vl\]
21 ** str p14, \[sp, #10, mul vl\]
22 ** str p15, \[sp, #11, mul vl\]
23 ** str z8, \[sp, #2, mul vl\]
24 ** str z9, \[sp, #3, mul vl\]
25 ** str z10, \[sp, #4, mul vl\]
26 ** str z11, \[sp, #5, mul vl\]
27 ** str z12, \[sp, #6, mul vl\]
28 ** str z13, \[sp, #7, mul vl\]
29 ** str z14, \[sp, #8, mul vl\]
30 ** str z15, \[sp, #9, mul vl\]
31 ** str z16, \[sp, #10, mul vl\]
32 ** str z17, \[sp, #11, mul vl\]
33 ** str z18, \[sp, #12, mul vl\]
34 ** str z19, \[sp, #13, mul vl\]
35 ** str z20, \[sp, #14, mul vl\]
36 ** str z21, \[sp, #15, mul vl\]
37 ** str z22, \[sp, #16, mul vl\]
38 ** str z23, \[sp, #17, mul vl\]
39 ** ptrue p0\.b, vl256
40 ** ldr z8, \[sp, #2, mul vl\]
41 ** ldr z9, \[sp, #3, mul vl\]
42 ** ldr z10, \[sp, #4, mul vl\]
43 ** ldr z11, \[sp, #5, mul vl\]
44 ** ldr z12, \[sp, #6, mul vl\]
45 ** ldr z13, \[sp, #7, mul vl\]
46 ** ldr z14, \[sp, #8, mul vl\]
47 ** ldr z15, \[sp, #9, mul vl\]
48 ** ldr z16, \[sp, #10, mul vl\]
49 ** ldr z17, \[sp, #11, mul vl\]
50 ** ldr z18, \[sp, #12, mul vl\]
51 ** ldr z19, \[sp, #13, mul vl\]
52 ** ldr z20, \[sp, #14, mul vl\]
53 ** ldr z21, \[sp, #15, mul vl\]
54 ** ldr z22, \[sp, #16, mul vl\]
55 ** ldr z23, \[sp, #17, mul vl\]
56 ** ldr p4, \[sp\]
57 ** ldr p5, \[sp, #1, mul vl\]
58 ** ldr p6, \[sp, #2, mul vl\]
59 ** ldr p7, \[sp, #3, mul vl\]
60 ** ldr p8, \[sp, #4, mul vl\]
61 ** ldr p9, \[sp, #5, mul vl\]
62 ** ldr p10, \[sp, #6, mul vl\]
63 ** ldr p11, \[sp, #7, mul vl\]
64 ** ldr p12, \[sp, #8, mul vl\]
65 ** ldr p13, \[sp, #9, mul vl\]
66 ** ldr p14, \[sp, #10, mul vl\]
67 ** ldr p15, \[sp, #11, mul vl\]
68 ** add sp, sp, x12
69 ** ret
70 */
71 svbool_t
72 test_1 (void)
73 {
74 asm volatile ("" :::
75 "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
76 "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15",
77 "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23",
78 "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
79 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
80 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15");
81 return svptrue_b8 ();
82 }
83
84 /*
85 ** test_2:
86 ** ptrue p0\.b, vl256
87 ** ret
88 */
89 svbool_t
90 test_2 (void)
91 {
92 asm volatile ("" :::
93 "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
94 "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
95 "p0", "p1", "p2", "p3");
96 return svptrue_b8 ();
97 }
98
99 /*
100 ** test_3:
101 ** sub sp, sp, #1536
102 ** str p5, \[sp\]
103 ** str p6, \[sp, #1, mul vl\]
104 ** str p11, \[sp, #2, mul vl\]
105 ** str z8, \[sp, #1, mul vl\]
106 ** str z13, \[sp, #2, mul vl\]
107 ** str z19, \[sp, #3, mul vl\]
108 ** str z20, \[sp, #4, mul vl\]
109 ** str z22, \[sp, #5, mul vl\]
110 ** ptrue p0\.b, vl256
111 ** ldr z8, \[sp, #1, mul vl\]
112 ** ldr z13, \[sp, #2, mul vl\]
113 ** ldr z19, \[sp, #3, mul vl\]
114 ** ldr z20, \[sp, #4, mul vl\]
115 ** ldr z22, \[sp, #5, mul vl\]
116 ** ldr p5, \[sp\]
117 ** ldr p6, \[sp, #1, mul vl\]
118 ** ldr p11, \[sp, #2, mul vl\]
119 ** add sp, sp, #?1536
120 ** ret
121 */
122 svbool_t
123 test_3 (void)
124 {
125 asm volatile ("" :::
126 "z8", "z13", "z19", "z20", "z22",
127 "p5", "p6", "p11");
128 return svptrue_b8 ();
129 }
130
131 /*
132 ** test_4:
133 ** sub sp, sp, #32
134 ** str p4, \[sp\]
135 ** ptrue p0\.b, vl256
136 ** ldr p4, \[sp\]
137 ** add sp, sp, #?32
138 ** ret
139 */
140 svbool_t
141 test_4 (void)
142 {
143 asm volatile ("" ::: "p4");
144 return svptrue_b8 ();
145 }
146
147 /*
148 ** test_5:
149 ** sub sp, sp, #256
150 ** str z15, \[sp\]
151 ** ptrue p0\.b, vl256
152 ** ldr z15, \[sp\]
153 ** add sp, sp, #?256
154 ** ret
155 */
156 svbool_t
157 test_5 (void)
158 {
159 asm volatile ("" ::: "z15");
160 return svptrue_b8 ();
161 }
162
163 /*
164 ** test_6:
165 ** sub sp, sp, #256
166 ** str z15, \[sp\]
167 ** mov z0\.b, #1
168 ** ldr z15, \[sp\]
169 ** add sp, sp, #?256
170 ** ret
171 */
172 svint8_t
173 test_6 (svbool_t p0, svbool_t p1, svbool_t p2, svbool_t p3)
174 {
175 asm volatile ("" :: "Upa" (p0), "Upa" (p1), "Upa" (p2), "Upa" (p3) : "z15");
176 return svdup_s8 (1);
177 }
178
179 /*
180 ** test_7:
181 ** sub sp, sp, #256
182 ** str z16, \[sp\]
183 ** ptrue p0\.b, vl256
184 ** ldr z16, \[sp\]
185 ** add sp, sp, #?256
186 ** ret
187 */
188 svbool_t
189 test_7 (void)
190 {
191 asm volatile ("" ::: "z16");
192 return svptrue_b8 ();
193 }