1  /* { dg-do assemble { target aarch64_asm_sve_ok } } */
       2  /* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
       3  
       4  #include <stdint.h>
       5  
       6  #define TEST_OP(TYPE) \
       7    TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a % 17; }
       8  
       9  #define TEST_TYPE(TYPE, SIZE) \
      10    typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
      11    TEST_OP (TYPE##SIZE)
      12  
      13  TEST_TYPE (int8_t, 32)
      14  TEST_TYPE (uint8_t, 32)
      15  
      16  TEST_TYPE (int8_t, 64)
      17  TEST_TYPE (uint8_t, 64)
      18  TEST_TYPE (int16_t, 64)
      19  TEST_TYPE (uint16_t, 64)
      20  
      21  TEST_TYPE (int8_t, 128)
      22  TEST_TYPE (uint8_t, 128)
      23  TEST_TYPE (int16_t, 128)
      24  TEST_TYPE (uint16_t, 128)
      25  TEST_TYPE (int32_t, 128)
      26  TEST_TYPE (uint32_t, 128)
      27  
      28  /* { dg-final { scan-assembler-times {\tsmulh\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
      29  /* { dg-final { scan-assembler-times {\tsmulh\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
      30  /* { dg-final { scan-assembler-times {\tsmulh\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
      31  
      32  /* { dg-final { scan-assembler-times {\tumulh\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
      33  /* { dg-final { scan-assembler-times {\tumulh\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
      34  /* { dg-final { scan-assembler-times {\tumulh\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */