1  /* { dg-do assemble { target aarch64_asm_sve_ok } } */
       2  /* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  /* Case 5.2: Interleaved elements and constants.  */ 
       6  
       7  #include <stdint.h>
       8  
       9  typedef int32_t vnx4si __attribute__((vector_size (32)));
      10  
      11  /*
      12  ** foo:
      13  **	...
      14  **	ld1w	(z[0-9]+\.s), p[0-9]+/z, \[x[0-9]+\]
      15  **	mov	(z[0-9]+\.s), w3
      16  **	insr	\2, w2
      17  **	insr	\2, w1
      18  **	insr	\2, w0
      19  **	zip1	\2, \2, \1
      20  **	...
      21  */
      22  __attribute__((noipa))
      23  vnx4si foo(int a, int b, int c, int d)
      24  {
      25    return (vnx4si) { a, 1, b, 2, c, 3, d, 4 }; 
      26  }