1  /* { dg-do assemble { target aarch64_asm_sve_ok } } */
       2  /* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
       3  
       4  #include <stdint.h>
       5  
       6  #define TEST_OP_IMM(TYPE, AMT) \
       7    TYPE test##_##TYPE##_##AMT (TYPE a, TYPE b) { return a + b * AMT; }
       8  
       9  #define TEST_OP(TYPE) \
      10    TEST_OP_IMM (TYPE, 2) \
      11    TEST_OP_IMM (TYPE, 4) \
      12    TEST_OP_IMM (TYPE, 8)
      13  
      14  #define TEST_TYPE(TYPE, SIZE) \
      15    typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
      16    TEST_OP (TYPE##SIZE)
      17  
      18  TEST_TYPE (int8_t, 32)
      19  TEST_TYPE (uint8_t, 32)
      20  
      21  TEST_TYPE (int8_t, 64)
      22  TEST_TYPE (uint8_t, 64)
      23  TEST_TYPE (int16_t, 64)
      24  TEST_TYPE (uint16_t, 64)
      25  
      26  /* These two can't use ADR.  */
      27  TEST_TYPE (int8_t, 128)
      28  TEST_TYPE (uint8_t, 128)
      29  TEST_TYPE (int16_t, 128)
      30  TEST_TYPE (uint16_t, 128)
      31  TEST_TYPE (int32_t, 128)
      32  TEST_TYPE (uint32_t, 128)
      33  
      34  /* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 6 } } */
      35  /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 6 } } */
      36  
      37  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl #?1\]\n} 4 } } */
      38  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl #?2\]\n} 4 } } */
      39  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl #?3\]\n} 4 } } */
      40  
      41  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl #?1\]\n} 6 } } */
      42  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl #?2\]\n} 6 } } */
      43  /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl #?3\]\n} 6 } } */