1  /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
       2  
       3  #include "test_sve_acle.h"
       4  
       5  /*
       6  ** mul_lane_0_f32_tied1:
       7  **	fmul	z0\.s, z0\.s, z1\.s\[0\]
       8  **	ret
       9  */
      10  TEST_UNIFORM_Z (mul_lane_0_f32_tied1, svfloat32_t,
      11  		z0 = svmul_lane_f32 (z0, z1, 0),
      12  		z0 = svmul_lane (z0, z1, 0))
      13  
      14  /*
      15  ** mul_lane_0_f32_tied2:
      16  **	fmul	z0\.s, z1\.s, z0\.s\[0\]
      17  **	ret
      18  */
      19  TEST_UNIFORM_Z (mul_lane_0_f32_tied2, svfloat32_t,
      20  		z0 = svmul_lane_f32 (z1, z0, 0),
      21  		z0 = svmul_lane (z1, z0, 0))
      22  
      23  /*
      24  ** mul_lane_0_f32_untied:
      25  **	fmul	z0\.s, z1\.s, z2\.s\[0\]
      26  **	ret
      27  */
      28  TEST_UNIFORM_Z (mul_lane_0_f32_untied, svfloat32_t,
      29  		z0 = svmul_lane_f32 (z1, z2, 0),
      30  		z0 = svmul_lane (z1, z2, 0))
      31  
      32  /*
      33  ** mul_lane_1_f32:
      34  **	fmul	z0\.s, z1\.s, z2\.s\[1\]
      35  **	ret
      36  */
      37  TEST_UNIFORM_Z (mul_lane_1_f32, svfloat32_t,
      38  		z0 = svmul_lane_f32 (z1, z2, 1),
      39  		z0 = svmul_lane (z1, z2, 1))
      40  
      41  /*
      42  ** mul_lane_2_f32:
      43  **	fmul	z0\.s, z1\.s, z2\.s\[2\]
      44  **	ret
      45  */
      46  TEST_UNIFORM_Z (mul_lane_2_f32, svfloat32_t,
      47  		z0 = svmul_lane_f32 (z1, z2, 2),
      48  		z0 = svmul_lane (z1, z2, 2))
      49  
      50  /*
      51  ** mul_lane_3_f32:
      52  **	fmul	z0\.s, z1\.s, z2\.s\[3\]
      53  **	ret
      54  */
      55  TEST_UNIFORM_Z (mul_lane_3_f32, svfloat32_t,
      56  		z0 = svmul_lane_f32 (z1, z2, 3),
      57  		z0 = svmul_lane (z1, z2, 3))
      58  
      59  /*
      60  ** mul_lane_z7_f32:
      61  **	fmul	z0\.s, z1\.s, z7\.s\[3\]
      62  **	ret
      63  */
      64  TEST_DUAL_Z (mul_lane_z7_f32, svfloat32_t, svfloat32_t,
      65  	     z0 = svmul_lane_f32 (z1, z7, 3),
      66  	     z0 = svmul_lane (z1, z7, 3))
      67  
      68  /*
      69  ** mul_lane_z8_f32:
      70  **	str	d8, \[sp, -16\]!
      71  **	mov	(z[0-7])\.d, z8\.d
      72  **	fmul	z0\.s, z1\.s, \1\.s\[3\]
      73  **	ldr	d8, \[sp\], 16
      74  **	ret
      75  */
      76  TEST_DUAL_LANE_REG (mul_lane_z8_f32, svfloat32_t, svfloat32_t, z8,
      77  		    z0 = svmul_lane_f32 (z1, z8, 3),
      78  		    z0 = svmul_lane (z1, z8, 3))