1  /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
       2  
       3  #include "test_sve_acle.h"
       4  
       5  /*
       6  ** ld1rq_s64_base:
       7  **	ld1rqd	z0\.d, p0/z, \[x0\]
       8  **	ret
       9  */
      10  TEST_LOAD (ld1rq_s64_base, svint64_t, int64_t,
      11  	   z0 = svld1rq_s64 (p0, x0),
      12  	   z0 = svld1rq (p0, x0))
      13  
      14  /*
      15  ** ld1rq_s64_index:
      16  **	ld1rqd	z0\.d, p0/z, \[x0, x1, lsl 3\]
      17  **	ret
      18  */
      19  TEST_LOAD (ld1rq_s64_index, svint64_t, int64_t,
      20  	   z0 = svld1rq_s64 (p0, x0 + x1),
      21  	   z0 = svld1rq (p0, x0 + x1))
      22  
      23  /*
      24  ** ld1rq_s64_1:
      25  **	add	(x[0-9]+), x0, #?8
      26  **	ld1rqd	z0\.d, p0/z, \[\1\]
      27  **	ret
      28  */
      29  TEST_LOAD (ld1rq_s64_1, svint64_t, int64_t,
      30  	   z0 = svld1rq_s64 (p0, x0 + 1),
      31  	   z0 = svld1rq (p0, x0 + 1))
      32  
      33  /*
      34  ** ld1rq_s64_2:
      35  **	ld1rqd	z0\.d, p0/z, \[x0, #?16\]
      36  **	ret
      37  */
      38  TEST_LOAD (ld1rq_s64_2, svint64_t, int64_t,
      39  	   z0 = svld1rq_s64 (p0, x0 + 2),
      40  	   z0 = svld1rq (p0, x0 + 2))
      41  
      42  /*
      43  ** ld1rq_s64_14:
      44  **	ld1rqd	z0\.d, p0/z, \[x0, #?112\]
      45  **	ret
      46  */
      47  TEST_LOAD (ld1rq_s64_14, svint64_t, int64_t,
      48  	   z0 = svld1rq_s64 (p0, x0 + 14),
      49  	   z0 = svld1rq (p0, x0 + 14))
      50  
      51  /*
      52  ** ld1rq_s64_16:
      53  **	add	(x[0-9]+), x0, #?128
      54  **	ld1rqd	z0\.d, p0/z, \[\1\]
      55  **	ret
      56  */
      57  TEST_LOAD (ld1rq_s64_16, svint64_t, int64_t,
      58  	   z0 = svld1rq_s64 (p0, x0 + 16),
      59  	   z0 = svld1rq (p0, x0 + 16))
      60  
      61  /*
      62  ** ld1rq_s64_m1:
      63  **	sub	(x[0-9]+), x0, #?8
      64  **	ld1rqd	z0\.d, p0/z, \[\1\]
      65  **	ret
      66  */
      67  TEST_LOAD (ld1rq_s64_m1, svint64_t, int64_t,
      68  	   z0 = svld1rq_s64 (p0, x0 - 1),
      69  	   z0 = svld1rq (p0, x0 - 1))
      70  
      71  /*
      72  ** ld1rq_s64_m2:
      73  **	ld1rqd	z0\.d, p0/z, \[x0, #?-16\]
      74  **	ret
      75  */
      76  TEST_LOAD (ld1rq_s64_m2, svint64_t, int64_t,
      77  	   z0 = svld1rq_s64 (p0, x0 - 2),
      78  	   z0 = svld1rq (p0, x0 - 2))
      79  
      80  /*
      81  ** ld1rq_s64_m16:
      82  **	ld1rqd	z0\.d, p0/z, \[x0, #?-128\]
      83  **	ret
      84  */
      85  TEST_LOAD (ld1rq_s64_m16, svint64_t, int64_t,
      86  	   z0 = svld1rq_s64 (p0, x0 - 16),
      87  	   z0 = svld1rq (p0, x0 - 16))
      88  
      89  /*
      90  ** ld1rq_s64_m18:
      91  **	sub	(x[0-9]+), x0, #?144
      92  **	ld1rqd	z0\.d, p0/z, \[\1\]
      93  **	ret
      94  */
      95  TEST_LOAD (ld1rq_s64_m18, svint64_t, int64_t,
      96  	   z0 = svld1rq_s64 (p0, x0 - 18),
      97  	   z0 = svld1rq (p0, x0 - 18))