1  /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
       2  
       3  #include "test_sve_acle.h"
       4  
       5  /*
       6  ** ld1rq_s32_base:
       7  **	ld1rqw	z0\.s, p0/z, \[x0\]
       8  **	ret
       9  */
      10  TEST_LOAD (ld1rq_s32_base, svint32_t, int32_t,
      11  	   z0 = svld1rq_s32 (p0, x0),
      12  	   z0 = svld1rq (p0, x0))
      13  
      14  /*
      15  ** ld1rq_s32_index:
      16  **	ld1rqw	z0\.s, p0/z, \[x0, x1, lsl 2\]
      17  **	ret
      18  */
      19  TEST_LOAD (ld1rq_s32_index, svint32_t, int32_t,
      20  	   z0 = svld1rq_s32 (p0, x0 + x1),
      21  	   z0 = svld1rq (p0, x0 + x1))
      22  
      23  /*
      24  ** ld1rq_s32_1:
      25  **	add	(x[0-9]+), x0, #?4
      26  **	ld1rqw	z0\.s, p0/z, \[\1\]
      27  **	ret
      28  */
      29  TEST_LOAD (ld1rq_s32_1, svint32_t, int32_t,
      30  	   z0 = svld1rq_s32 (p0, x0 + 1),
      31  	   z0 = svld1rq (p0, x0 + 1))
      32  
      33  /*
      34  ** ld1rq_s32_2:
      35  **	add	(x[0-9]+), x0, #?8
      36  **	ld1rqw	z0\.s, p0/z, \[\1\]
      37  **	ret
      38  */
      39  TEST_LOAD (ld1rq_s32_2, svint32_t, int32_t,
      40  	   z0 = svld1rq_s32 (p0, x0 + 2),
      41  	   z0 = svld1rq (p0, x0 + 2))
      42  
      43  /*
      44  ** ld1rq_s32_3:
      45  **	add	(x[0-9]+), x0, #?12
      46  **	ld1rqw	z0\.s, p0/z, \[\1\]
      47  **	ret
      48  */
      49  TEST_LOAD (ld1rq_s32_3, svint32_t, int32_t,
      50  	   z0 = svld1rq_s32 (p0, x0 + 3),
      51  	   z0 = svld1rq (p0, x0 + 3))
      52  
      53  /*
      54  ** ld1rq_s32_4:
      55  **	ld1rqw	z0\.s, p0/z, \[x0, #?16\]
      56  **	ret
      57  */
      58  TEST_LOAD (ld1rq_s32_4, svint32_t, int32_t,
      59  	   z0 = svld1rq_s32 (p0, x0 + 4),
      60  	   z0 = svld1rq (p0, x0 + 4))
      61  
      62  /*
      63  ** ld1rq_s32_28:
      64  **	ld1rqw	z0\.s, p0/z, \[x0, #?112\]
      65  **	ret
      66  */
      67  TEST_LOAD (ld1rq_s32_28, svint32_t, int32_t,
      68  	   z0 = svld1rq_s32 (p0, x0 + 28),
      69  	   z0 = svld1rq (p0, x0 + 28))
      70  
      71  /*
      72  ** ld1rq_s32_32:
      73  **	add	(x[0-9]+), x0, #?128
      74  **	ld1rqw	z0\.s, p0/z, \[\1\]
      75  **	ret
      76  */
      77  TEST_LOAD (ld1rq_s32_32, svint32_t, int32_t,
      78  	   z0 = svld1rq_s32 (p0, x0 + 32),
      79  	   z0 = svld1rq (p0, x0 + 32))
      80  
      81  /*
      82  ** ld1rq_s32_m1:
      83  **	sub	(x[0-9]+), x0, #?4
      84  **	ld1rqw	z0\.s, p0/z, \[\1\]
      85  **	ret
      86  */
      87  TEST_LOAD (ld1rq_s32_m1, svint32_t, int32_t,
      88  	   z0 = svld1rq_s32 (p0, x0 - 1),
      89  	   z0 = svld1rq (p0, x0 - 1))
      90  
      91  /*
      92  ** ld1rq_s32_m2:
      93  **	sub	(x[0-9]+), x0, #?8
      94  **	ld1rqw	z0\.s, p0/z, \[\1\]
      95  **	ret
      96  */
      97  TEST_LOAD (ld1rq_s32_m2, svint32_t, int32_t,
      98  	   z0 = svld1rq_s32 (p0, x0 - 2),
      99  	   z0 = svld1rq (p0, x0 - 2))
     100  
     101  /*
     102  ** ld1rq_s32_m3:
     103  **	sub	(x[0-9]+), x0, #?12
     104  **	ld1rqw	z0\.s, p0/z, \[\1\]
     105  **	ret
     106  */
     107  TEST_LOAD (ld1rq_s32_m3, svint32_t, int32_t,
     108  	   z0 = svld1rq_s32 (p0, x0 - 3),
     109  	   z0 = svld1rq (p0, x0 - 3))
     110  
     111  /*
     112  ** ld1rq_s32_m4:
     113  **	ld1rqw	z0\.s, p0/z, \[x0, #?-16\]
     114  **	ret
     115  */
     116  TEST_LOAD (ld1rq_s32_m4, svint32_t, int32_t,
     117  	   z0 = svld1rq_s32 (p0, x0 - 4),
     118  	   z0 = svld1rq (p0, x0 - 4))
     119  
     120  /*
     121  ** ld1rq_s32_m32:
     122  **	ld1rqw	z0\.s, p0/z, \[x0, #?-128\]
     123  **	ret
     124  */
     125  TEST_LOAD (ld1rq_s32_m32, svint32_t, int32_t,
     126  	   z0 = svld1rq_s32 (p0, x0 - 32),
     127  	   z0 = svld1rq (p0, x0 - 32))
     128  
     129  /*
     130  ** ld1rq_s32_m36:
     131  **	sub	(x[0-9]+), x0, #?144
     132  **	ld1rqw	z0\.s, p0/z, \[\1\]
     133  **	ret
     134  */
     135  TEST_LOAD (ld1rq_s32_m36, svint32_t, int32_t,
     136  	   z0 = svld1rq_s32 (p0, x0 - 36),
     137  	   z0 = svld1rq (p0, x0 - 36))