1  /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
       2  /* { dg-require-effective-target aarch64_asm_bf16_ok }  */
       3  /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
       4  
       5  #include "test_sve_acle.h"
       6  
       7  /*
       8  ** bfmlalt_lane_0_f32_tied1:
       9  **	bfmlalt	z0\.s, z4\.h, z5\.h\[0\]
      10  **	ret
      11  */
      12  TEST_DUAL_Z (bfmlalt_lane_0_f32_tied1, svfloat32_t, svbfloat16_t,
      13  	     z0 = svbfmlalt_lane_f32 (z0, z4, z5, 0),
      14  	     z0 = svbfmlalt_lane (z0, z4, z5, 0))
      15  
      16  /*
      17  ** bfmlalt_lane_0_f32_tied2:
      18  **	mov	(z[0-9]+)\.d, z0\.d
      19  **	movprfx	z0, z4
      20  **	bfmlalt	z0\.s, \1\.h, z1\.h\[0\]
      21  **	ret
      22  */
      23  TEST_DUAL_Z_REV (bfmlalt_lane_0_f32_tied2, svfloat32_t, svbfloat16_t,
      24  		 z0_res = svbfmlalt_lane_f32 (z4, z0, z1, 0),
      25  		 z0_res = svbfmlalt_lane (z4, z0, z1, 0))
      26  
      27  /*
      28  ** bfmlalt_lane_0_f32_tied3:
      29  **	mov	(z[0-9]+)\.d, z0\.d
      30  **	movprfx	z0, z4
      31  **	bfmlalt	z0\.s, z1\.h, \1\.h\[0\]
      32  **	ret
      33  */
      34  TEST_DUAL_Z_REV (bfmlalt_lane_0_f32_tied3, svfloat32_t, svbfloat16_t,
      35  		 z0_res = svbfmlalt_lane_f32 (z4, z1, z0, 0),
      36  		 z0_res = svbfmlalt_lane (z4, z1, z0, 0))
      37  
      38  /*
      39  ** bfmlalt_lane_0_f32_untied:
      40  **	movprfx	z0, z1
      41  **	bfmlalt	z0\.s, z4\.h, z5\.h\[0\]
      42  **	ret
      43  */
      44  TEST_DUAL_Z (bfmlalt_lane_0_f32_untied, svfloat32_t, svbfloat16_t,
      45  	     z0 = svbfmlalt_lane_f32 (z1, z4, z5, 0),
      46  	     z0 = svbfmlalt_lane (z1, z4, z5, 0))
      47  
      48  /*
      49  ** bfmlalt_lane_1_f32:
      50  **	bfmlalt	z0\.s, z4\.h, z5\.h\[1\]
      51  **	ret
      52  */
      53  TEST_DUAL_Z (bfmlalt_lane_1_f32, svfloat32_t, svbfloat16_t,
      54  	     z0 = svbfmlalt_lane_f32 (z0, z4, z5, 1),
      55  	     z0 = svbfmlalt_lane (z0, z4, z5, 1))
      56  
      57  /*
      58  ** bfmlalt_lane_7_f32:
      59  **	bfmlalt	z0\.s, z4\.h, z5\.h\[7\]
      60  **	ret
      61  */
      62  TEST_DUAL_Z (bfmlalt_lane_7_f32, svfloat32_t, svbfloat16_t,
      63  	     z0 = svbfmlalt_lane_f32 (z0, z4, z5, 7),
      64  	     z0 = svbfmlalt_lane (z0, z4, z5, 7))
      65  
      66  /*
      67  ** bfmlalt_lane_z8_f32:
      68  **	str	d8, \[sp, -16\]!
      69  **	mov	(z[0-7])\.d, z8\.d
      70  **	bfmlalt	z0\.s, z1\.h, \1\.h\[1\]
      71  **	ldr	d8, \[sp\], 16
      72  **	ret
      73  */
      74  TEST_DUAL_LANE_REG (bfmlalt_lane_z8_f32, svfloat32_t, svbfloat16_t, z8,
      75  		    z0 = svbfmlalt_lane_f32 (z0, z1, z8, 1),
      76  		    z0 = svbfmlalt_lane (z0, z1, z8, 1))
      77  
      78  /*
      79  ** bfmlalt_lane_z16_f32:
      80  **	mov	(z[0-7])\.d, z16\.d
      81  **	bfmlalt	z0\.s, z1\.h, \1\.h\[1\]
      82  **	ret
      83  */
      84  TEST_DUAL_LANE_REG (bfmlalt_lane_z16_f32, svfloat32_t, svbfloat16_t, z16,
      85  		    z0 = svbfmlalt_lane_f32 (z0, z1, z16, 1),
      86  		    z0 = svbfmlalt_lane (z0, z1, z16, 1))