1  /* { dg-do compile } */
       2  /* { dg-require-effective-target supports_stack_clash_protection } */
       3  /* { dg-options "-O3 -fopenmp-simd -march=armv8-a+sve -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
       4  
       5  /* Invoke X (P##n) for n in [0, 7].  */
       6  #define REPEAT8(X, P) \
       7    X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7)
       8  
       9  /* Invoke X (n) for all octal n in [0, 39].  */
      10  #define REPEAT40(X) \
      11    REPEAT8 (X, 0) REPEAT8 (X, 1)  REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4)
      12  
      13  /* Expect vector work to be done, with spilling of vector registers.  */
      14  void
      15  f2 (int x[40][100], int *y)
      16  {
      17    /* Try to force some spilling.  */
      18  #define DECLARE(N) int y##N = y[N];
      19    REPEAT40 (DECLARE);
      20  #pragma omp simd
      21    for (int i = 0; i < 100; ++i)
      22      {
      23  #define INC(N) x[N][i] += y##N;
      24        REPEAT40 (INC);
      25      }
      26  }
      27  
      28  /* SVE spill, requires probing as vector size is unknown at compile time.  */
      29  
      30  /* { dg-final { scan-assembler-times {str\s+xzr, \[sp, 0\]} 1 } } */
      31  /* { dg-final { scan-assembler-times {cmp\s+x[0-9]+, 61440} 1 } } */
      32  /* { dg-final { scan-assembler-times {sub\s+x[0-9]+, x[0-9]+, 61440} 1 } } */