1  /* { dg-do compile } */
       2  /* { dg-additional-options "-mharden-sls=blr -mbranch-protection=bti" } */
       3  /*
       4     Ensure that the SLS hardening of BLR leaves no BLR instructions.
       5     Here we also check that there are no BR instructions with anything except an
       6     x16 or x17 register.  This is because a `BTI c` instruction can be branched
       7     to using a BLR instruction using any register, but can only be branched to
       8     with a BR using an x16 or x17 register.
       9    */
      10  typedef int (foo) (int, int);
      11  typedef void (bar) (int, int);
      12  struct sls_testclass {
      13      foo *x;
      14      bar *y;
      15      int left;
      16      int right;
      17  };
      18  
      19  /* We test both RTL patterns for a call which returns a value and a call which
      20     does not.  */
      21  int blr_call_value (struct sls_testclass x)
      22  {
      23    int retval = x.x(x.left, x.right);
      24    if (retval % 10)
      25      return 100;
      26    return 9;
      27  }
      28  
      29  int blr_call (struct sls_testclass x)
      30  {
      31    x.y(x.left, x.right);
      32    if (x.left % 10)
      33      return 100;
      34    return 9;
      35  }
      36  
      37  /* { dg-final { scan-assembler-not {\tblr\t} } } */
      38  /* { dg-final { scan-assembler-not {\tbr\tx(?!16|17)} } } */
      39  /* { dg-final { scan-assembler {\tbr\tx(16|17)} } } */
      40