1  /* Test the vmulxs_laneq_f32 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float32_t __attribute__ ((noinline))
      11  test_vmulxs_laneq_f32_lane0 (float32_t vec1_1, float32x4_t vec1_2)
      12  {
      13    return vmulxs_laneq_f32 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  float32_t __attribute__ ((noinline))
      17  test_vmulxs_laneq_f32_lane1 (float32_t vec1_1, float32x4_t vec1_2)
      18  {
      19    return vmulxs_laneq_f32 (vec1_1, vec1_2, 1);
      20  }
      21  
      22  float32_t __attribute__ ((noinline))
      23  test_vmulxs_laneq_f32_lane2 (float32_t vec1_1, float32x4_t vec1_2)
      24  {
      25    return vmulxs_laneq_f32 (vec1_1, vec1_2, 2);
      26  }
      27  
      28  float32_t __attribute__ ((noinline))
      29  test_vmulxs_laneq_f32_lane3 (float32_t vec1_1, float32x4_t vec1_2)
      30  {
      31    return vmulxs_laneq_f32 (vec1_1, vec1_2, 3);
      32  }
      33  
      34  #define PASS_ARRAY(...) {__VA_ARGS__}
      35  
      36  #define SETUP_VEC(V1_D, V2_D, EXP1, EXP2, EXP3, EXP4, I)		\
      37    void set_and_test_case##I ()						\
      38    {									\
      39      float32_t vec1 = V1_D;						\
      40      float32_t vec2_data[] =  V2_D;					\
      41      float32x4_t vec2 = vld1q_f32 (vec2_data);				\
      42      float32_t expected_lane0 = EXP1;					\
      43      float32_t expected_lane1 = EXP2;					\
      44      float32_t expected_lane2 = EXP3;					\
      45      float32_t expected_lane3 = EXP4;					\
      46      float32_t actual_lane0 = test_vmulxs_laneq_f32_lane0 (vec1, vec2);	\
      47      if (actual_lane0 != expected_lane0)					\
      48        abort ();								\
      49      float32_t actual_lane1 = test_vmulxs_laneq_f32_lane1 (vec1, vec2);	\
      50      if (actual_lane1 != expected_lane1)					\
      51        abort ();								\
      52      float32_t actual_lane2 = test_vmulxs_laneq_f32_lane2 (vec1, vec2);	\
      53      if (actual_lane2 != expected_lane2)					\
      54        abort ();								\
      55      float32_t actual_lane3 = test_vmulxs_laneq_f32_lane3 (vec1, vec2);	\
      56      if (actual_lane3 != expected_lane3)					\
      57        abort ();								\
      58    }									\
      59  
      60  float32_t v1 = 3.14159265359;
      61  float32_t v2 = 1.383894;
      62  float32_t v3 = -2.71828;
      63  float32_t v4 = -3.4891931;
      64  
      65  float32_t v5 = 0.0;
      66  float32_t v6 = -0.0;
      67  float32_t v7 = __builtin_huge_valf ();
      68  float32_t v8 = -__builtin_huge_valf ();
      69  
      70  SETUP_VEC (v1, PASS_ARRAY (v1, v2, v3, v4), v1*v1, v1*v2, v3*v1, v1*v4, 1)
      71  SETUP_VEC (v5, PASS_ARRAY (v5, v6, v7, v8), 0.0, -0.0, 2.0, -2.0, 2)
      72  SETUP_VEC (v6, PASS_ARRAY (v5, v6, v7, v8), -0.0, 0.0, -2.0, 2.0, 3)
      73  
      74  int
      75  main (void)
      76  {
      77    set_and_test_case1 ();
      78    set_and_test_case2 ();
      79    set_and_test_case3 ();
      80    return 0;
      81  }
      82  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]\n" 1 } } */
      83  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[1\\\]\n" 1 } } */
      84  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[2\\\]\n" 1 } } */
      85  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[3\\\]\n" 1 } } */