1  /* Test the vmulxq_laneq_f64 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float64x2_t __attribute__ ((noinline))
      11  test_vmulxq_laneq_f64_lane0 (float64x2_t vec1_1, float64x2_t vec1_2)
      12  {
      13    return vmulxq_laneq_f64 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  float64x2_t __attribute__ ((noinline))
      17  test_vmulxq_laneq_f64_lane1 (float64x2_t vec1_1, float64x2_t vec1_2)
      18  {
      19    return vmulxq_laneq_f64 (vec1_1, vec1_2, 1);
      20  }
      21  
      22  #define PASS_ARRAY(...) {__VA_ARGS__}
      23  
      24  #define SETUP_VEC(V1_D, V2_D, EXP0, EXP1, I)				\
      25    void set_and_test_case##I ()						\
      26    {									\
      27      int i;								\
      28      float64_t vec1_data[] = V1_D;					\
      29      float64x2_t vec1 = vld1q_f64 (vec1_data);				\
      30      float64_t vec2_data[] =  V2_D;					\
      31      float64x2_t vec2 = vld1q_f64 (vec2_data);				\
      32  									\
      33      float64_t expected_lane0[] = EXP0;					\
      34      float64_t expected_lane1[] = EXP1;					\
      35  									\
      36      float64x2_t actual_lane0_v =					\
      37        test_vmulxq_laneq_f64_lane0 (vec1, vec2);				\
      38      float64_t actual_lane0[2];						\
      39      vst1q_f64 (actual_lane0, actual_lane0_v);				\
      40      for (i = 0; i < 2; ++i)						\
      41        if (actual_lane0[i] != expected_lane0[i])				\
      42  	abort ();							\
      43  									\
      44      float64x2_t actual_lane1_v =					\
      45        test_vmulxq_laneq_f64_lane1 (vec1, vec2);				\
      46      float64_t actual_lane1[2];						\
      47      vst1q_f64 (actual_lane1, actual_lane1_v);				\
      48      for (i = 0; i < 2; ++i)						\
      49        if (actual_lane1[i] != expected_lane1[i])				\
      50  	abort ();							\
      51  									\
      52    }									\
      53  
      54  float64_t v1 = 3.14159265359;
      55  float64_t v2 = 1.383894;
      56  
      57  float64_t v3 = 0.0;
      58  float64_t v4 = -0.0;
      59  float64_t v5 = __builtin_huge_val ();
      60  float64_t v6 = -__builtin_huge_val ();
      61  
      62  float64_t spec = __builtin_huge_val () * __builtin_huge_val ();
      63  
      64  SETUP_VEC (PASS_ARRAY (v1, v2), PASS_ARRAY (v1, v2), PASS_ARRAY (v1*v1, v2*v1),
      65  	   PASS_ARRAY (v1*v2, v2*v2), 1)
      66  
      67  SETUP_VEC (PASS_ARRAY (v3, v4), PASS_ARRAY (v5, v6), PASS_ARRAY (2.0, -2.0),
      68  	   PASS_ARRAY (-2.0, 2.0), 2)
      69  
      70  int
      71  main (void)
      72  {
      73    set_and_test_case1 ();
      74    set_and_test_case2 ();
      75    return 0;
      76  }
      77  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.\[dD\]\\\[0\\\]\n" 1 } } */
      78  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.\[dD\]\\\[1\\\]\n" 1 } } */