1  /* Test the vmulxq_lane_f64 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float64x2_t __attribute__ ((noinline))
      11  test_vmulxq_lane_f64_lane0 (float64x2_t vec1_1, float64x1_t vec1_2)
      12  {
      13    return vmulxq_lane_f64 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  #define PASS_ARRAY(...) {__VA_ARGS__}
      17  
      18  #define SETUP_VEC(V1_D, V2_D, EXP0, I)					\
      19    void set_and_test_case##I ()						\
      20    {									\
      21      int i;								\
      22      float64_t vec1_data[] = V1_D;					\
      23      float64x2_t vec1 = vld1q_f64 (vec1_data);				\
      24      float64_t vec2_data[] =  V2_D;					\
      25      float64x1_t vec2 = vld1_f64 (vec2_data);				\
      26  									\
      27      float64_t expected_lane0[] = EXP0;					\
      28      float64x2_t actual_lane0_v						\
      29        = test_vmulxq_lane_f64_lane0 (vec1, vec2);			\
      30      float64_t actual_lane0[2];						\
      31      vst1q_f64 (actual_lane0, actual_lane0_v);				\
      32      for (i = 0; i < 1; ++i)						\
      33        if (actual_lane0[i] != expected_lane0[i])				\
      34  	abort ();							\
      35    }									\
      36  
      37  float64_t v1 = 3.14159265359;
      38  float64_t v2 = 1.383894;
      39  
      40  float64_t v3 = __builtin_huge_val ();
      41  float64_t v4 = -__builtin_huge_val ();
      42  
      43  float64_t v5 = 0.0;
      44  float64_t v6 = -0.0;
      45  
      46  
      47  SETUP_VEC (PASS_ARRAY (v1, v2), PASS_ARRAY (v1), PASS_ARRAY (v1*v1, v2*v1), 1)
      48  
      49  SETUP_VEC (PASS_ARRAY (v3, v4), PASS_ARRAY (v5), PASS_ARRAY (2.0, -2.0), 2)
      50  
      51  SETUP_VEC (PASS_ARRAY (v3, v4), PASS_ARRAY (v6), PASS_ARRAY (-2.0, 2.0), 3)
      52  
      53  int
      54  main (void)
      55  {
      56    set_and_test_case1 ();
      57    set_and_test_case2 ();
      58    set_and_test_case3 ();
      59    return 0;
      60  }
      61  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.\[dD\]\\\[0\\\]\n" 1 } } */