1  /* Test the vmulxq_lane_f32 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float32x4_t __attribute__ ((noinline))
      11  test_vmulxq_lane_f32_lane0 (float32x4_t vec1_1, float32x2_t vec1_2)
      12  {
      13    return vmulxq_lane_f32 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  float32x4_t __attribute__ ((noinline))
      17  test_vmulxq_lane_f32_lane1 (float32x4_t vec1_1, float32x2_t vec1_2)
      18  {
      19    return vmulxq_lane_f32 (vec1_1, vec1_2, 1);
      20  }
      21  
      22  #define PASS_ARRAY(...) {__VA_ARGS__}
      23  
      24  #define SETUP_VEC(V1_D, V2_D, EXP0, EXP1, I)				\
      25    void set_and_test_case##I ()						\
      26    {									\
      27      int i;								\
      28      float32_t vec1_data[] = V1_D;					\
      29      float32x4_t vec1 = vld1q_f32 (vec1_data);				\
      30      float32_t vec2_data[] =  V2_D;					\
      31      float32x2_t vec2 = vld1_f32 (vec2_data);				\
      32  									\
      33      float32_t expected_lane0[] = EXP0;					\
      34      float32_t expected_lane1[] = EXP1;					\
      35  									\
      36      float32x4_t actual_lane0_v =					\
      37        test_vmulxq_lane_f32_lane0 (vec1, vec2);				\
      38      float32_t actual_lane0[4];						\
      39      vst1q_f32 (actual_lane0, actual_lane0_v);				\
      40      for (i = 0; i < 4; ++i)						\
      41        if (actual_lane0[i] != expected_lane0[i])				\
      42  	abort ();							\
      43  									\
      44      float32x4_t actual_lane1_v =					\
      45        test_vmulxq_lane_f32_lane1 (vec1, vec2);				\
      46      float32_t actual_lane1[4];						\
      47      vst1q_f32 (actual_lane1, actual_lane1_v);				\
      48      for (i = 0; i < 4; ++i)						\
      49        if (actual_lane1[i] != expected_lane1[i])				\
      50  	abort ();							\
      51    }									\
      52  
      53  float32_t v1 = 3.14159265359;
      54  float32_t v2 = 1.383894;
      55  float32_t v3 = -2.71828;
      56  float32_t v4 = -3.4891931;
      57  
      58  float32_t v5 = 0.0;
      59  float32_t v6 = -0.0;
      60  float32_t v7 = __builtin_huge_valf ();
      61  float32_t v8 = -__builtin_huge_valf ();
      62  
      63  SETUP_VEC (PASS_ARRAY (v1, v2, v3, v4), PASS_ARRAY (v1, v2),
      64  	   PASS_ARRAY (v1*v1, v2*v1, v3*v1, v4*v1),
      65  	   PASS_ARRAY (v1*v2, v2*v2, v3*v2, v4*v2), 1)
      66  
      67  SETUP_VEC (PASS_ARRAY (v5, v6, v7, v8), PASS_ARRAY (v5, v6),
      68  	   PASS_ARRAY (0.0, -0.0, 2.0, -2.0),
      69  	   PASS_ARRAY (-0.0, 0.0, -2.0, 2.0), 2)
      70  
      71  int
      72  main (void)
      73  {
      74    set_and_test_case1 ();
      75    set_and_test_case2 ();
      76    return 0;
      77  }
      78  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
      79  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[1\\\]\n" 1 } } */