1  /* Test the vmulxd_lane_f64 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float64_t __attribute__ ((noinline))
      11  test_vmulxd_lane_f64_lane0 (float64_t vec1_1, float64x1_t vec1_2)
      12  {
      13    return vmulxd_lane_f64 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  #define PASS_ARRAY(...) {__VA_ARGS__}
      17  
      18  #define SETUP_VEC(V1_D, V2_D, EXP1, I)					\
      19    void set_and_test_case##I ()						\
      20    {									\
      21      float64_t vec1 = V1_D;						\
      22      float64_t vec2_data[] =  V2_D;					\
      23      float64x1_t vec2 = vld1_f64 (vec2_data);				\
      24      float64_t expected_lane0 = EXP1;					\
      25      float64_t actual_lane0 = test_vmulxd_lane_f64_lane0 (vec1, vec2);	\
      26      if (actual_lane0 != expected_lane0)					\
      27        abort ();								\
      28    }									\
      29  
      30  float64_t v1 = 3.14159265359;
      31  float64_t v2 = 1.383894;
      32  
      33  float64_t v4 = 0.0;
      34  float64_t v5 = -0.0;
      35  float64_t v6 = __builtin_huge_val ();
      36  float64_t v7 = -__builtin_huge_val ();
      37  
      38  SETUP_VEC (v1, PASS_ARRAY (v2), v1*v2, 1)
      39  SETUP_VEC (v4, PASS_ARRAY (v6), 2.0, 2)
      40  SETUP_VEC (v4, PASS_ARRAY (v7), -2.0, 3)
      41  SETUP_VEC (v5, PASS_ARRAY (v6), -2.0, 4)
      42  SETUP_VEC (v5, PASS_ARRAY (v7), 2.0, 5)
      43  
      44  int
      45  main (void)
      46  {
      47    set_and_test_case1 ();
      48    set_and_test_case2 ();
      49    set_and_test_case3 ();
      50    set_and_test_case4 ();
      51    set_and_test_case5 ();
      52    return 0;
      53  }
      54  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?(?:\[vV\]\[0-9\]+\.\[dD\]\\\[0\\\]|\[dD\]\[0-9\])\n" 1 } } */