1  /* Test the vmulx_laneq_f32 AArch64 SIMD intrinsic.  */
       2  
       3  /* { dg-do run } */
       4  /* { dg-options "-save-temps -O3" } */
       5  
       6  #include "arm_neon.h"
       7  
       8  extern void abort (void);
       9  
      10  float32x2_t __attribute__ ((noinline))
      11  test_vmulx_laneq_f32_lane0 (float32x2_t vec1_1, float32x4_t vec1_2)
      12  {
      13    return vmulx_laneq_f32 (vec1_1, vec1_2, 0);
      14  }
      15  
      16  float32x2_t __attribute__ ((noinline))
      17  test_vmulx_laneq_f32_lane1 (float32x2_t vec1_1, float32x4_t vec1_2)
      18  {
      19    return vmulx_laneq_f32 (vec1_1, vec1_2, 1);
      20  }
      21  
      22  float32x2_t __attribute__ ((noinline))
      23  test_vmulx_laneq_f32_lane2 (float32x2_t vec1_1, float32x4_t vec1_2)
      24  {
      25    return vmulx_laneq_f32 (vec1_1, vec1_2, 2);
      26  }
      27  
      28  float32x2_t __attribute__ ((noinline))
      29  test_vmulx_laneq_f32_lane3 (float32x2_t vec1_1, float32x4_t vec1_2)
      30  {
      31    return vmulx_laneq_f32 (vec1_1, vec1_2, 3);
      32  }
      33  
      34  #define PASS_ARRAY(...) {__VA_ARGS__}
      35  
      36  #define SETUP_VEC(V1_D, V2_D, EXP0, EXP1, EXP2, EXP3, I)		\
      37    void set_and_test_case##I ()						\
      38    {									\
      39      float32_t vec1_data[] = V1_D;					\
      40      float32x2_t vec1 = vld1_f32 (vec1_data);				\
      41      float32_t vec2_data[] =  V2_D;					\
      42      float32x4_t vec2 = vld1q_f32 (vec2_data);				\
      43  									\
      44      float32_t expected_lane0[] = EXP0;					\
      45      float32_t expected_lane1[] = EXP1;					\
      46      float32_t expected_lane2[] = EXP2;					\
      47      float32_t expected_lane3[] = EXP3;					\
      48  									\
      49      float32x2_t actual_lane0_v =					\
      50        test_vmulx_laneq_f32_lane0 (vec1, vec2);				\
      51      float32_t actual_lane0[2];						\
      52      vst1_f32 (actual_lane0, actual_lane0_v);				\
      53      if (actual_lane0[0] != expected_lane0[0]				\
      54  	|| actual_lane0[1] != expected_lane0[1])			\
      55        abort ();								\
      56  									\
      57      float32x2_t actual_lane1_v =					\
      58        test_vmulx_laneq_f32_lane1 (vec1, vec2);				\
      59      float32_t actual_lane1[2];						\
      60      vst1_f32 (actual_lane1, actual_lane1_v);				\
      61      if (actual_lane1[0] != expected_lane1[0]				\
      62  	|| actual_lane1[1] != expected_lane1[1])			\
      63        abort ();								\
      64  									\
      65      float32x2_t actual_lane2_v =					\
      66        test_vmulx_laneq_f32_lane2 (vec1, vec2);				\
      67      float32_t actual_lane2[2];						\
      68      vst1_f32 (actual_lane2, actual_lane2_v);				\
      69      if (actual_lane2[0] != expected_lane2[0]				\
      70  	|| actual_lane2[1] != expected_lane2[1])			\
      71        abort ();								\
      72  									\
      73      float32x2_t actual_lane3_v =					\
      74        test_vmulx_laneq_f32_lane3 (vec1, vec2);				\
      75      float32_t actual_lane3[2];						\
      76      vst1_f32 (actual_lane3, actual_lane3_v);				\
      77      if (actual_lane3[0] != expected_lane3[0]				\
      78  	|| actual_lane3[1] != expected_lane3[1])			\
      79        abort ();								\
      80  									\
      81    }									\
      82  
      83  float32_t v1 = 3.14159265359;
      84  float32_t v2 = 1.383894;
      85  float32_t v3 = -2.71828;
      86  float32_t v4 = -3.4891931;
      87  
      88  float32_t v5 = 0.0;
      89  float32_t v6 = -0.0;
      90  float32_t v7 = __builtin_huge_valf ();
      91  float32_t v8 = -__builtin_huge_valf ();
      92  
      93  SETUP_VEC (PASS_ARRAY (v1, v2), PASS_ARRAY (v1, v2, v3, v4),
      94  	   PASS_ARRAY (v1*v1, v1*v2), PASS_ARRAY (v1*v2, v2*v2),
      95  	   PASS_ARRAY (v1*v3, v2*v3), PASS_ARRAY (v1*v4, v2*v4), 1)
      96  
      97  SETUP_VEC (PASS_ARRAY (v5, v6), PASS_ARRAY (v5, v6, v7, v8),
      98  	   PASS_ARRAY (0.0, -0.0), PASS_ARRAY (-0.0, 0.0),
      99  	   PASS_ARRAY (2.0, -2.0), PASS_ARRAY (-2.0, 2.0), 2)
     100  
     101  int
     102  main (void)
     103  {
     104    set_and_test_case1 ();
     105    set_and_test_case2 ();
     106    return 0;
     107  }
     108  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
     109  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[1\\\]\n" 1 } } */
     110  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[2\\\]\n" 1 } } */
     111  /* { dg-final { scan-assembler-times "fmulx\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[3\\\]\n" 1 } } */