1  /* { dg-do compile } */
       2  /* { dg-options "-O3" } */
       3  
       4  typedef short int __attribute__ ((vector_size (16))) v8hi;
       5  
       6  v8hi
       7  mla8hi (v8hi v0, v8hi v1, short int v2)
       8  {
       9    /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */
      10    return v0 + v1 * v2;
      11  }
      12  
      13  
      14  v8hi
      15  mls8hi (v8hi v0, v8hi v1, short int v2)
      16  {
      17    /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */
      18    return v0 - v1 * v2;
      19  }
      20  
      21  typedef short int __attribute__ ((vector_size (8))) v4hi;
      22  
      23  v4hi
      24  mla4hi (v4hi v0, v4hi v1, short int v2)
      25  {
      26    /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */
      27    return v0 + v1 * v2;
      28  }
      29  
      30  v4hi
      31  mls4hi (v4hi v0, v4hi v1, short int v2)
      32  {
      33    /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */
      34    return v0 - v1 * v2;
      35  }
      36  
      37  typedef int __attribute__ ((vector_size (16))) v4si;
      38  
      39  v4si
      40  mla4si (v4si v0, v4si v1, int v2)
      41  {
      42    /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */
      43    return v0 + v1 * v2;
      44  }
      45  
      46  v4si
      47  mls4si (v4si v0, v4si v1, int v2)
      48  {
      49    /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */
      50    return v0 - v1 * v2;
      51  }
      52  
      53  typedef int __attribute__((vector_size (8))) v2si;
      54  
      55  v2si
      56  mla2si (v2si v0, v2si v1, int v2)
      57  {
      58    /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */
      59    return v0 + v1 * v2;
      60  }
      61  
      62  v2si
      63  mls2si (v2si v0, v2si v1, int v2)
      64  {
      65    /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */
      66    return v0 - v1 * v2;
      67  }