1 /* { dg-do run } */
2 /* { dg-options "-O2 -fno-inline -save-temps" } */
3
4 extern void abort ();
5
6 #define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
7 #define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
8
9 typedef unsigned long long int UInt64x1;
10 typedef long long int Int64x1;
11 typedef unsigned int UInt32x1;
12 typedef int Int32x1;
13
14 UInt64x1
15 test_lshift_left_sisd_di (UInt64x1 b, UInt64x1 c)
16 {
17 UInt64x1 a;
18
19 force_simd_di (b);
20 force_simd_di (c);
21 a = b << 8;
22 a = a << c;
23 force_simd_di (a);
24 return a;
25 }
26 /* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
27 /* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
28
29 UInt32x1
30 test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c)
31 {
32 UInt32x1 a;
33
34 force_simd_si (b);
35 force_simd_si (c);
36 a = b << 4;
37 a = a << c;
38 force_simd_si (a);
39 return a;
40 }
41 /* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
42 /* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */
43
44 UInt64x1
45 test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c)
46 {
47 UInt64x1 a;
48
49 force_simd_di (b);
50 force_simd_di (c);
51 a = b >> 8;
52 a = a >> c;
53 force_simd_di (a);
54 return a;
55 }
56 /* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
57 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
58 /* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
59
60 UInt64x1
61 test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c)
62 {
63 UInt32x1 a;
64
65 force_simd_si (b);
66 force_simd_si (c);
67 a = b >> 4;
68 a = a >> c;
69 force_simd_si (a);
70 return a;
71 }
72 /* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
73 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
74 /* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
75
76 Int64x1
77 test_ashift_right_sisd_di (Int64x1 b, Int64x1 c)
78 {
79 Int64x1 a;
80
81 force_simd_di (b);
82 force_simd_di (c);
83 a = b >> 8;
84 a = a >> c;
85 force_simd_di (a);
86 return a;
87 }
88 /* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
89 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
90 /* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
91
92 Int32x1
93 test_ashift_right_sisd_si (Int32x1 b, Int32x1 c)
94 {
95 Int32x1 a;
96
97 force_simd_si (b);
98 force_simd_si (c);
99 a = b >> 4;
100 a = a >> c;
101 force_simd_si (a);
102 return a;
103 }
104 /* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
105 /* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */
106 /* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
107
108
109 /* The following are to make sure if the integer instructions lsl/lsr/asr are
110 generated in non-vector scenarios */
111
112 UInt64x1
113 test_lshift_left_int_di (UInt64x1 b, UInt64x1 c)
114 {
115 UInt64x1 a;
116
117 a = b << 8;
118 a = a << c;
119 return a;
120 }
121 /* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
122 /* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
123
124 UInt32x1
125 test_lshift_left_int_si (UInt32x1 b, UInt32x1 c)
126 {
127 UInt32x1 a;
128
129 a = b << 4;
130 a = a << c;
131 return a;
132 }
133 /* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
134 /* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
135
136 UInt64x1
137 test_lshift_right_int_di (UInt64x1 b, UInt64x1 c)
138 {
139 UInt64x1 a;
140
141 a = b >> 8;
142 a = a >> c;
143 return a;
144 }
145 /* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
146 /* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
147
148 UInt32x1
149 test_lshift_right_int_si (UInt32x1 b, UInt32x1 c)
150 {
151 UInt32x1 a;
152
153 a = b >> 4;
154 a = a >> c;
155 return a;
156 }
157 /* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
158 /* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
159
160 Int64x1
161 test_ashift_right_int_di (Int64x1 b, Int64x1 c)
162 {
163 Int64x1 a;
164
165 a = b >> 8;
166 a = a >> c;
167 return a;
168 }
169 /* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
170 /* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
171
172 Int32x1
173 test_ashift_right_int_si (Int32x1 b, Int32x1 c)
174 {
175 Int32x1 a;
176
177 a = b >> 4;
178 a = a >> c;
179 return a;
180 }
181 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
182 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
183
184 #define CHECK(var,val) \
185 do \
186 { \
187 if (var != val) \
188 abort(); \
189 } \
190 while(0)
191
192 UInt64x1 x = 0xC01dDeadBeefFaceull;
193 UInt32x1 y = 0xDeadBeef;
194
195 int
196 main ()
197 {
198 x = test_lshift_left_sisd_di (x, 8);
199 CHECK (x, 0xdeadbeefface0000ull);
200 x = test_lshift_right_int_di (x, 8);
201 CHECK (x, 0x0000deadbeeffaceull);
202 x = test_lshift_right_sisd_di (x, 8);
203 CHECK (x, 0x00000000deadbeefull);
204 x = test_lshift_left_int_di (x, 8);
205 CHECK (x, 0x0000deadbeef0000ull);
206 x = ~x;
207 x = test_ashift_right_int_di (x, 8);
208 CHECK (x, 0xffffffff21524110ull);
209 x = test_ashift_right_sisd_di (x, 8);
210 CHECK (x, 0xffffffffffff2152ull);
211
212 y = test_lshift_left_sisd_si (y, 4);
213 CHECK (y, 0xadbeef00);
214 y = test_lshift_right_int_si (y, 4);
215 CHECK (y, 0x00adbeef);
216 y = test_lshift_right_sisd_si (y, 4);
217 CHECK (y, 0x0000adbe);
218 y = test_lshift_left_int_si (y, 4);
219 CHECK (y, 0x00adbe00);
220 y = ~y;
221 y = test_ashift_right_int_si (y, 4);
222 CHECK (y, 0xffff5241);
223 y = test_ashift_right_sisd_si (y, 4);
224 CHECK (y, 0xffffff52);
225
226 return 0;
227 }
228