1 /* { dg-do assemble } */
2 /* { dg-options "-O -mtune=neoverse-v1 --save-temps" } */
3 /* { dg-final { check-function-bodies "**" "" "" } } */
4
5 #pragma GCC target "+nothing+nosimd+fp"
6
7 typedef unsigned char v16qi __attribute__((vector_size(16)));
8
9 /*
10 ** fpr_to_fpr:
11 ** sub sp, sp, #16
12 ** str q1, \[sp\]
13 ** ldr q0, \[sp\]
14 ** add sp, sp, #?16
15 ** ret
16 */
17 v16qi
18 fpr_to_fpr (v16qi q0, v16qi q1)
19 {
20 return q1;
21 }
22
23 /*
24 ** gpr_to_fpr: { target aarch64_little_endian }
25 ** fmov d0, x0
26 ** fmov v0.d\[1\], x1
27 ** ret
28 */
29 /*
30 ** gpr_to_fpr: { target aarch64_big_endian }
31 ** fmov d0, x1
32 ** fmov v0.d\[1\], x0
33 ** ret
34 */
35 v16qi
36 gpr_to_fpr ()
37 {
38 register v16qi x0 asm ("x0");
39 asm volatile ("" : "=r" (x0));
40 return x0;
41 }
42
43 /*
44 ** zero_to_fpr:
45 ** fmov d0, xzr
46 ** ret
47 */
48 v16qi
49 zero_to_fpr ()
50 {
51 return (v16qi) {};
52 }
53
54 /*
55 ** fpr_to_gpr: { target aarch64_little_endian }
56 ** (
57 ** fmov x0, d0
58 ** fmov x1, v0.d\[1\]
59 ** |
60 ** fmov x1, v0.d\[1\]
61 ** fmov x0, d0
62 ** )
63 ** ret
64 */
65 /*
66 ** fpr_to_gpr: { target aarch64_big_endian }
67 ** (
68 ** fmov x1, d0
69 ** fmov x0, v0.d\[1\]
70 ** |
71 ** fmov x0, v0.d\[1\]
72 ** fmov x1, d0
73 ** )
74 ** ret
75 */
76 void
77 fpr_to_gpr (v16qi q0)
78 {
79 register v16qi x0 asm ("x0");
80 x0 = q0;
81 asm volatile ("" :: "r" (x0));
82 }
83
84 /*
85 ** gpr_to_gpr:
86 ** (
87 ** mov x0, x2
88 ** mov x1, x3
89 ** |
90 ** mov x1, x3
91 ** mov x0, x2
92 ** )
93 ** ret
94 */
95 void
96 gpr_to_gpr ()
97 {
98 register v16qi x0 asm ("x0");
99 register v16qi x2 asm ("x2");
100 asm volatile ("" : "=r" (x2));
101 x0 = x2;
102 asm volatile ("" :: "r" (x0));
103 }