1  /* { dg-do run } */
       2  /* { dg-options "-O3 --save-temps" } */
       3  
       4  #include <arm_neon.h>
       5  
       6  #define DELTA 0.0001
       7  
       8  extern double fabs (double);
       9  
      10  extern void abort (void);
      11  
      12  #define TEST_VMLS(q1, q2, size, in1_lanes, in2_lanes)			\
      13  static void								\
      14  __attribute__((noipa,noinline))						\
      15  test_vfms##q1##_lane##q2##_f##size (float##size##_t * res,		\
      16  				   const float##size##_t *in1,		\
      17  				   const float##size##_t *in2)		\
      18  {									\
      19    float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res);		\
      20    float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1);		\
      21    float##size##x##in2_lanes##_t c;					\
      22    if (in2_lanes > 1)							\
      23      {									\
      24        c = vld1##q2##_f##size (in2);					\
      25        a = vfms##q1##_lane##q2##_f##size (a, b, c, 1);			\
      26      }									\
      27    else									\
      28      {									\
      29        c = vld1##q2##_f##size (in2 + 1);					\
      30        a = vfms##q1##_lane##q2##_f##size (a, b, c, 0);			\
      31      }									\
      32    vst1##q1##_f##size (res, a);						\
      33  }
      34  
      35  #define BUILD_VARS(width, n_lanes, n_half_lanes)		\
      36  TEST_VMLS ( ,  , width, n_half_lanes, n_half_lanes)		\
      37  TEST_VMLS (q,  , width, n_lanes, n_half_lanes)			\
      38  TEST_VMLS ( , q, width, n_half_lanes, n_lanes)			\
      39  TEST_VMLS (q, q, width, n_lanes, n_lanes)			\
      40  
      41  BUILD_VARS (32, 4, 2)
      42  BUILD_VARS (64, 2, 1)
      43  
      44  #define POOL2 {0.0, 1.0}
      45  #define POOL4 {0.0, 1.0, 2.0, 3.0}
      46  #define EMPTY2 {0.0, 0.0}
      47  #define EMPTY4 {0.0, 0.0, 0.0, 0.0}
      48  
      49  #define BUILD_TEST(size, lanes)					\
      50  static void							\
      51  test_f##size (void)						\
      52  {								\
      53    int i;							\
      54    float##size##_t pool[lanes] = POOL##lanes;			\
      55    float##size##_t res[lanes] = EMPTY##lanes;			\
      56    float##size##_t res2[lanes] = EMPTY##lanes;			\
      57    float##size##_t res3[lanes] = EMPTY##lanes;			\
      58    float##size##_t res4[lanes] = EMPTY##lanes;			\
      59  								\
      60    /* Forecfully avoid optimization.  */				\
      61    asm volatile ("" : : : "memory");				\
      62    test_vfms_lane_f##size (res, pool, pool);			\
      63    asm volatile ("" : :"Q" (res) : "memory");			\
      64    for (i = 0; i < lanes / 2; i++)				\
      65      if (fabs (res[i] + pool[i]) > DELTA)			\
      66        abort ();							\
      67  								\
      68    /* Forecfully avoid optimization.  */				\
      69    test_vfmsq_lane_f##size (res2, pool, pool);			\
      70    asm volatile ("" : :"Q" (res2) : "memory");			\
      71    for (i = 0; i < lanes; i++)					\
      72      if (fabs (res2[i] + pool[i]) > DELTA)			\
      73        abort ();							\
      74  								\
      75    /* Forecfully avoid optimization.  */				\
      76    test_vfms_laneq_f##size (res3, pool, pool);			\
      77    asm volatile ("" : :"Q" (res3) : "memory");			\
      78    for (i = 0; i < lanes / 2; i++)				\
      79      if (fabs (res3[i] + pool[i]) > DELTA)			\
      80        abort ();							\
      81  								\
      82    /* Forecfully avoid optimization.  */				\
      83    test_vfmsq_laneq_f##size (res4, pool, pool);			\
      84    asm volatile ("" : :"Q" (res4) : "memory");			\
      85    for (i = 0; i < lanes; i++)					\
      86      if (fabs (res4[i] + pool[i]) > DELTA)			\
      87        abort ();							\
      88  }
      89  
      90  BUILD_TEST (32, 4)
      91  BUILD_TEST (64, 2)
      92  
      93  int
      94  main (int argc, char **argv)
      95  {
      96    test_f32 ();
      97    test_f64 ();
      98    return 0;
      99  }
     100  
     101  /* vfms_laneq_f32.
     102     vfms_lane_f32.  */
     103  /* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
     104  
     105  /* vfmsq_lane_f32.
     106     vfmsq_laneq_f32.  */
     107  /* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
     108  
     109  /* vfms_lane_f64.
     110     vfms_laneq_f64.  */
     111  /* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 { target aarch64_big_endian } } } */
     112  /* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 2 { target aarch64_little_endian } } } */
     113  
     114  /* vfmsq_lane_f64.
     115     vfmsq_laneq_f64.  */
     116  /* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 { target aarch64_big_endian } } } */
     117  /* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 { target aarch64_little_endian } } } */
     118  
     119