1  /* { dg-do compile } */
       2  /* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
       3  
       4  long v = 0;
       5  
       6  long
       7  atomic_fetch_add_RELAXED (long a)
       8  {
       9    return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
      10  }
      11  
      12  long
      13  atomic_fetch_sub_RELAXED (long a)
      14  {
      15    return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
      16  }
      17  
      18  long
      19  atomic_fetch_and_RELAXED (long a)
      20  {
      21    return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
      22  }
      23  
      24  long
      25  atomic_fetch_nand_RELAXED (long a)
      26  {
      27    return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
      28  }
      29  
      30  long
      31  atomic_fetch_xor_RELAXED (long a)
      32  {
      33    return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
      34  }
      35  
      36  long
      37  atomic_fetch_or_RELAXED (long a)
      38  {
      39    return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
      40  }
      41  
      42  /* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
      43  /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
      44  /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
      45  /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */