(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
aarch64/
advsimd-intrinsics/
vtrn_half.c
       1  /* { dg-do run } */
       2  /* { dg-skip-if "" { arm*-*-* } } */
       3  
       4  #include <arm_neon.h>
       5  #include "arm-neon-ref.h"
       6  #include "compute-ref-data.h"
       7  
       8  /* Expected results.  */
       9  VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf2, 0x11,
      10  				       0xf4, 0x11, 0xf6, 0x11 };
      11  VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff2, 0x22 };
      12  VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
      13  VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
      14  VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
      15  					0xf4, 0x55, 0xf6, 0x55 };
      16  VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
      17  VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
      18  VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
      19  VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
      20  					0xf4, 0x55, 0xf6, 0x55 };
      21  VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
      22  VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
      23  #if defined (FP16_SUPPORTED)
      24  VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
      25  					       0xcb00, 0x4b4d };
      26  #endif
      27  VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf2, 0x11,
      28  					0xf4, 0x11, 0xf6, 0x11,
      29  					0xf8, 0x11, 0xfa, 0x11,
      30  					0xfc, 0x11, 0xfe, 0x11 };
      31  VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff2, 0x22,
      32  					0xfff4, 0x22, 0xfff6, 0x22 };
      33  VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
      34  					0xfffffff2, 0x33 };
      35  VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
      36  					0x44 };
      37  VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
      38  					 0xf4, 0x55, 0xf6, 0x55,
      39  					 0xf8, 0x55, 0xfa, 0x55,
      40  					 0xfc, 0x55, 0xfe, 0x55 };
      41  VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
      42  					 0xfff4, 0x66, 0xfff6, 0x66 };
      43  VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
      44  					 0xfffffff2, 0x77 };
      45  VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
      46  					 0x88 };
      47  VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
      48  					 0xf4, 0x55, 0xf6, 0x55,
      49  					 0xf8, 0x55, 0xfa, 0x55,
      50  					 0xfc, 0x55, 0xfe, 0x55 };
      51  VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
      52  					 0xfff4, 0x66, 0xfff6, 0x66 };
      53  #if defined (FP16_SUPPORTED)
      54  VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
      55  					       0xcb00, 0x4b4d,
      56  					       0xca00, 0x4b4d,
      57  					       0xc900, 0x4b4d };
      58  #endif
      59  VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
      60  					   0xc1600000, 0x42073333 };
      61  
      62  #define TEST_MSG "VTRN1"
      63  void exec_vtrn_half (void)
      64  {
      65  #define TEST_VTRN(PART, Q, T1, T2, W, N)		\
      66    VECT_VAR(vector_res, T1, W, N) =			\
      67      vtrn##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
      68  		       VECT_VAR(vector2, T1, W, N));	\
      69    vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
      70  
      71  #define TEST_VTRN1(Q, T1, T2, W, N) TEST_VTRN(1, Q, T1, T2, W, N)
      72  
      73    /* Input vector can only have 64 bits.  */
      74    DECL_VARIABLE_ALL_VARIANTS(vector);
      75    DECL_VARIABLE_ALL_VARIANTS(vector2);
      76  
      77    DECL_VARIABLE_ALL_VARIANTS(vector_res);
      78  
      79    clean_results ();
      80    /* We don't have vtrn1_T64x1, so set expected to the clean value.  */
      81    CLEAN(expected, int, 64, 1);
      82    CLEAN(expected, uint, 64, 1);
      83  
      84    TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
      85  #if defined (FP16_SUPPORTED)
      86    VLOAD(vector, buffer, , float, f, 16, 4);
      87    VLOAD(vector, buffer, q, float, f, 16, 8);
      88  #endif
      89    VLOAD(vector, buffer, , float, f, 32, 2);
      90    VLOAD(vector, buffer, q, float, f, 32, 4);
      91    VLOAD(vector, buffer, q, float, f, 64, 2);
      92  
      93    /* Choose arbitrary initialization values.  */
      94    VDUP(vector2, , int, s, 8, 8, 0x11);
      95    VDUP(vector2, , int, s, 16, 4, 0x22);
      96    VDUP(vector2, , int, s, 32, 2, 0x33);
      97    VDUP(vector2, , uint, u, 8, 8, 0x55);
      98    VDUP(vector2, , uint, u, 16, 4, 0x66);
      99    VDUP(vector2, , uint, u, 32, 2, 0x77);
     100    VDUP(vector2, , poly, p, 8, 8, 0x55);
     101    VDUP(vector2, , poly, p, 16, 4, 0x66);
     102  #if defined (FP16_SUPPORTED)
     103    VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
     104  #endif
     105    VDUP(vector2, , float, f, 32, 2, 33.6f);
     106  
     107    VDUP(vector2, q, int, s, 8, 16, 0x11);
     108    VDUP(vector2, q, int, s, 16, 8, 0x22);
     109    VDUP(vector2, q, int, s, 32, 4, 0x33);
     110    VDUP(vector2, q, int, s, 64, 2, 0x44);
     111    VDUP(vector2, q, uint, u, 8, 16, 0x55);
     112    VDUP(vector2, q, uint, u, 16, 8, 0x66);
     113    VDUP(vector2, q, uint, u, 32, 4, 0x77);
     114    VDUP(vector2, q, uint, u, 64, 2, 0x88);
     115    VDUP(vector2, q, poly, p, 8, 16, 0x55);
     116    VDUP(vector2, q, poly, p, 16, 8, 0x66);
     117  #if defined (FP16_SUPPORTED)
     118    VDUP (vector2, q, float, f, 16, 8, 14.6f);
     119  #endif
     120    VDUP(vector2, q, float, f, 32, 4, 33.8f);
     121    VDUP(vector2, q, float, f, 64, 2, 33.8f);
     122  
     123    TEST_VTRN1(, int, s, 8, 8);
     124    TEST_VTRN1(, int, s, 16, 4);
     125    TEST_VTRN1(, int, s, 32, 2);
     126    TEST_VTRN1(, uint, u, 8, 8);
     127    TEST_VTRN1(, uint, u, 16, 4);
     128    TEST_VTRN1(, uint, u, 32, 2);
     129    TEST_VTRN1(, poly, p, 8, 8);
     130    TEST_VTRN1(, poly, p, 16, 4);
     131  #if defined (FP16_SUPPORTED)
     132    TEST_VTRN1(, float, f, 16, 4);
     133  #endif
     134    TEST_VTRN1(, float, f, 32, 2);
     135  
     136    TEST_VTRN1(q, int, s, 8, 16);
     137    TEST_VTRN1(q, int, s, 16, 8);
     138    TEST_VTRN1(q, int, s, 32, 4);
     139    TEST_VTRN1(q, int, s, 64, 2);
     140    TEST_VTRN1(q, uint, u, 8, 16);
     141    TEST_VTRN1(q, uint, u, 16, 8);
     142    TEST_VTRN1(q, uint, u, 32, 4);
     143    TEST_VTRN1(q, uint, u, 64, 2);
     144    TEST_VTRN1(q, poly, p, 8, 16);
     145    TEST_VTRN1(q, poly, p, 16, 8);
     146  #if defined (FP16_SUPPORTED)
     147    TEST_VTRN1(q, float, f, 16, 8);
     148  #endif
     149    TEST_VTRN1(q, float, f, 32, 4);
     150    TEST_VTRN1(q, float, f, 64, 2);
     151  
     152  #if defined (FP16_SUPPORTED)
     153    CHECK_RESULTS (TEST_MSG, "");
     154  #else
     155    CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
     156  #endif
     157  
     158  #undef TEST_MSG
     159  #define TEST_MSG "VTRN2"
     160  
     161  #define TEST_VTRN2(Q, T1, T2, W, N) TEST_VTRN(2, Q, T1, T2, W, N)
     162  
     163  /* Expected results.  */
     164  VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11,
     165  					0xf5, 0x11, 0xf7, 0x11 };
     166  VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0x22, 0xfff3, 0x22 };
     167  VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
     168  VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
     169  VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
     170  					 0xf5, 0x55, 0xf7, 0x55 };
     171  VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
     172  VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
     173  VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
     174  VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
     175  					 0xf5, 0x55, 0xf7, 0x55 };
     176  VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
     177  VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
     178  #if defined (FP16_SUPPORTED)
     179  VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d,
     180  						0xca80, 0x4b4d };
     181  #endif
     182  VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0x11, 0xf3, 0x11,
     183  					 0xf5, 0x11, 0xf7, 0x11,
     184  					 0xf9, 0x11, 0xfb, 0x11,
     185  					 0xfd, 0x11, 0xff, 0x11 };
     186  VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0x22, 0xfff3, 0x22,
     187  					 0xfff5, 0x22, 0xfff7, 0x22 };
     188  VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33,
     189  					 0xfffffff3, 0x33 };
     190  VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
     191  					 0x44 };
     192  VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
     193  					  0xf5, 0x55, 0xf7, 0x55,
     194  					  0xf9, 0x55, 0xfb, 0x55,
     195  					  0xfd, 0x55, 0xff, 0x55 };
     196  VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
     197  					  0xfff5, 0x66, 0xfff7, 0x66 };
     198  VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77,
     199  					  0xfffffff3, 0x77 };
     200  VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
     201  					  0x88 };
     202  VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
     203  					  0xf5, 0x55, 0xf7, 0x55,
     204  					  0xf9, 0x55, 0xfb, 0x55,
     205  					  0xfd, 0x55, 0xff, 0x55 };
     206  VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
     207  					  0xfff5, 0x66, 0xfff7, 0x66 };
     208  #if defined (FP16_SUPPORTED)
     209  VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0x4b4d,
     210  						0xca80, 0x4b4d,
     211  						0xc980, 0x4b4d,
     212  						0xc880, 0x4b4d };
     213  #endif
     214  VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0x42073333,
     215  					    0xc1500000, 0x42073333 };
     216    clean_results ();
     217    CLEAN(expected2, int, 64, 1);
     218    CLEAN(expected2, uint, 64, 1);
     219  
     220    TEST_VTRN2(, int, s, 8, 8);
     221    TEST_VTRN2(, int, s, 16, 4);
     222    TEST_VTRN2(, int, s, 32, 2);
     223    TEST_VTRN2(, uint, u, 8, 8);
     224    TEST_VTRN2(, uint, u, 16, 4);
     225    TEST_VTRN2(, uint, u, 32, 2);
     226    TEST_VTRN2(, poly, p, 8, 8);
     227    TEST_VTRN2(, poly, p, 16, 4);
     228  #if defined (FP16_SUPPORTED)
     229    TEST_VTRN2(, float, f, 16, 4);
     230  #endif
     231    TEST_VTRN2(, float, f, 32, 2);
     232  
     233    TEST_VTRN2(q, int, s, 8, 16);
     234    TEST_VTRN2(q, int, s, 16, 8);
     235    TEST_VTRN2(q, int, s, 32, 4);
     236    TEST_VTRN2(q, int, s, 64, 2);
     237    TEST_VTRN2(q, uint, u, 8, 16);
     238    TEST_VTRN2(q, uint, u, 16, 8);
     239    TEST_VTRN2(q, uint, u, 32, 4);
     240    TEST_VTRN2(q, uint, u, 64, 2);
     241    TEST_VTRN2(q, poly, p, 8, 16);
     242    TEST_VTRN2(q, poly, p, 16, 8);
     243  #if defined (FP16_SUPPORTED)
     244    TEST_VTRN2(q, float, f, 16, 8);
     245  #endif
     246    TEST_VTRN2(q, float, f, 32, 4);
     247    TEST_VTRN2(q, float, f, 64, 2);
     248  
     249    CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
     250  #if defined (FP16_SUPPORTED)
     251    CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
     252    CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
     253  #endif
     254  }
     255  
     256  int main (void)
     257  {
     258    exec_vtrn_half ();
     259    return 0;
     260  }