(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
aarch64/
advsimd-intrinsics/
vshrn_n.c
       1  #include <arm_neon.h>
       2  #include "arm-neon-ref.h"
       3  #include "compute-ref-data.h"
       4  
       5  /* Expected results.  */
       6  VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
       7  				       0xfa, 0xfa, 0xfb, 0xfb };
       8  VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff8, 0xfff9, 0xfff9 };
       9  VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
      10  VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfc, 0xfc, 0xfc, 0xfc,
      11  					0xfd, 0xfd, 0xfd, 0xfd };
      12  VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe };
      13  VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffffe, 0xfffffffe };
      14  
      15  #define TEST_MSG "VSHRN_N"
      16  void exec_vshrn_n (void)
      17  {
      18    /* Basic test: y=vshrn_n(x,v), then store the result.  */
      19  #define TEST_VSHRN_N(T1, T2, W, W2, N, V)				\
      20    VECT_VAR(vector_res, T1, W2, N) =					\
      21      vshrn_n_##T2##W(VECT_VAR(vector, T1, W, N),				\
      22  		    V);							\
      23    vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
      24  
      25    /* vector is twice as large as vector_res.  */
      26    DECL_VARIABLE(vector, int, 16, 8);
      27    DECL_VARIABLE(vector, int, 32, 4);
      28    DECL_VARIABLE(vector, int, 64, 2);
      29    DECL_VARIABLE(vector, uint, 16, 8);
      30    DECL_VARIABLE(vector, uint, 32, 4);
      31    DECL_VARIABLE(vector, uint, 64, 2);
      32  
      33    DECL_VARIABLE(vector_res, int, 8, 8);
      34    DECL_VARIABLE(vector_res, int, 16, 4);
      35    DECL_VARIABLE(vector_res, int, 32, 2);
      36    DECL_VARIABLE(vector_res, uint, 8, 8);
      37    DECL_VARIABLE(vector_res, uint, 16, 4);
      38    DECL_VARIABLE(vector_res, uint, 32, 2);
      39  
      40    clean_results ();
      41  
      42    VLOAD(vector, buffer, q, int, s, 16, 8);
      43    VLOAD(vector, buffer, q, int, s, 32, 4);
      44    VLOAD(vector, buffer, q, int, s, 64, 2);
      45    VLOAD(vector, buffer, q, uint, u, 16, 8);
      46    VLOAD(vector, buffer, q, uint, u, 32, 4);
      47    VLOAD(vector, buffer, q, uint, u, 64, 2);
      48  
      49    /* Choose shift amount arbitrarily.  */
      50    TEST_VSHRN_N(int, s, 16, 8, 8, 1);
      51    TEST_VSHRN_N(int, s, 32, 16, 4, 1);
      52    TEST_VSHRN_N(int, s, 64, 32, 2, 2);
      53    TEST_VSHRN_N(uint, u, 16, 8, 8, 2);
      54    TEST_VSHRN_N(uint, u, 32, 16, 4, 3);
      55    TEST_VSHRN_N(uint, u, 64, 32, 2, 3);
      56  
      57  #define CMT ""
      58    CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
      59    CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
      60    CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
      61    CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
      62    CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
      63    CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
      64  }
      65  
      66  int main (void)
      67  {
      68    exec_vshrn_n ();
      69    return 0;
      70  }