1 #include <arm_neon.h>
2 #include "arm-neon-ref.h"
3 #include "compute-ref-data.h"
4
5 /* Expected results. */
6 VECT_VAR_DECL(expected,int,8,8) [] = { 0xf9, 0xfa, 0xfb, 0xfc,
7 0xfd, 0xfe, 0xff, 0x0 };
8 VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
9 VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffd, 0xfffffffe };
10 VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
11 VECT_VAR_DECL(expected,uint,8,8) [] = { 0x5, 0x6, 0x7, 0x8,
12 0x9, 0xa, 0xb, 0xc };
13 VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffd, 0xfffe, 0xffff, 0x0 };
14 VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff4, 0xfffffff5 };
15 VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
16 VECT_VAR_DECL(expected,int,8,16) [] = { 0xf9, 0xfa, 0xfb, 0xfc,
17 0xfd, 0xfe, 0xff, 0x0,
18 0x1, 0x2, 0x3, 0x4,
19 0x5, 0x6, 0x7, 0x8 };
20 VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
21 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
22 VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffd, 0xfffffffe,
23 0xffffffff, 0x0 };
24 VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0, 0xfffffffffffffff1 };
25 VECT_VAR_DECL(expected,uint,8,16) [] = { 0x5, 0x6, 0x7, 0x8,
26 0x9, 0xa, 0xb, 0xc,
27 0xd, 0xe, 0xf, 0x10,
28 0x11, 0x12, 0x13, 0x14 };
29 VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
30 0x1, 0x2, 0x3, 0x4 };
31 VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff4, 0xfffffff5,
32 0xfffffff6, 0xfffffff7 };
33 VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
34 0xfffffffffffffff1 };
35
36 /* Expected results with max input and shift by 1. */
37 VECT_VAR_DECL(expected_max_sh1,int,8,8) [] = { 0x40, 0x40, 0x40, 0x40,
38 0x40, 0x40, 0x40, 0x40 };
39 VECT_VAR_DECL(expected_max_sh1,int,16,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
40 VECT_VAR_DECL(expected_max_sh1,int,32,2) [] = { 0x40000000, 0x40000000 };
41 VECT_VAR_DECL(expected_max_sh1,int,64,1) [] = { 0x4000000000000000 };
42 VECT_VAR_DECL(expected_max_sh1,uint,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
43 0x80, 0x80, 0x80, 0x80 };
44 VECT_VAR_DECL(expected_max_sh1,uint,16,4) [] = { 0x8000, 0x8000,
45 0x8000, 0x8000 };
46 VECT_VAR_DECL(expected_max_sh1,uint,32,2) [] = { 0x80000000, 0x80000000 };
47 VECT_VAR_DECL(expected_max_sh1,uint,64,1) [] = { 0x8000000000000000 };
48 VECT_VAR_DECL(expected_max_sh1,int,8,16) [] = { 0x40, 0x40, 0x40, 0x40,
49 0x40, 0x40, 0x40, 0x40,
50 0x40, 0x40, 0x40, 0x40,
51 0x40, 0x40, 0x40, 0x40 };
52 VECT_VAR_DECL(expected_max_sh1,int,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000,
53 0x4000, 0x4000, 0x4000, 0x4000 };
54 VECT_VAR_DECL(expected_max_sh1,int,32,4) [] = { 0x40000000, 0x40000000,
55 0x40000000, 0x40000000 };
56 VECT_VAR_DECL(expected_max_sh1,int,64,2) [] = { 0x4000000000000000,
57 0x4000000000000000 };
58 VECT_VAR_DECL(expected_max_sh1,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
59 0x80, 0x80, 0x80, 0x80,
60 0x80, 0x80, 0x80, 0x80,
61 0x80, 0x80, 0x80, 0x80 };
62 VECT_VAR_DECL(expected_max_sh1,uint,16,8) [] = { 0x8000, 0x8000,
63 0x8000, 0x8000,
64 0x8000, 0x8000,
65 0x8000, 0x8000 };
66 VECT_VAR_DECL(expected_max_sh1,uint,32,4) [] = { 0x80000000, 0x80000000,
67 0x80000000, 0x80000000 };
68 VECT_VAR_DECL(expected_max_sh1,uint,64,2) [] = { 0x8000000000000000,
69 0x8000000000000000 };
70
71 /* Expected results with max input and shift by 3. */
72 VECT_VAR_DECL(expected_max_sh3,int,8,8) [] = { 0x10, 0x10, 0x10, 0x10,
73 0x10, 0x10, 0x10, 0x10 };
74 VECT_VAR_DECL(expected_max_sh3,int,16,4) [] = { 0x1000, 0x1000, 0x1000, 0x1000 };
75 VECT_VAR_DECL(expected_max_sh3,int,32,2) [] = { 0x10000000, 0x10000000 };
76 VECT_VAR_DECL(expected_max_sh3,int,64,1) [] = { 0x1000000000000000 };
77 VECT_VAR_DECL(expected_max_sh3,uint,8,8) [] = { 0x20, 0x20, 0x20, 0x20,
78 0x20, 0x20, 0x20, 0x20 };
79 VECT_VAR_DECL(expected_max_sh3,uint,16,4) [] = { 0x2000, 0x2000,
80 0x2000, 0x2000 };
81 VECT_VAR_DECL(expected_max_sh3,uint,32,2) [] = { 0x20000000, 0x20000000 };
82 VECT_VAR_DECL(expected_max_sh3,uint,64,1) [] = { 0x2000000000000000 };
83 VECT_VAR_DECL(expected_max_sh3,int,8,16) [] = { 0x10, 0x10, 0x10, 0x10,
84 0x10, 0x10, 0x10, 0x10,
85 0x10, 0x10, 0x10, 0x10,
86 0x10, 0x10, 0x10, 0x10 };
87 VECT_VAR_DECL(expected_max_sh3,int,16,8) [] = { 0x1000, 0x1000, 0x1000, 0x1000,
88 0x1000, 0x1000, 0x1000, 0x1000 };
89 VECT_VAR_DECL(expected_max_sh3,int,32,4) [] = { 0x10000000, 0x10000000,
90 0x10000000, 0x10000000 };
91 VECT_VAR_DECL(expected_max_sh3,int,64,2) [] = { 0x1000000000000000,
92 0x1000000000000000 };
93 VECT_VAR_DECL(expected_max_sh3,uint,8,16) [] = { 0x20, 0x20, 0x20, 0x20,
94 0x20, 0x20, 0x20, 0x20,
95 0x20, 0x20, 0x20, 0x20,
96 0x20, 0x20, 0x20, 0x20 };
97 VECT_VAR_DECL(expected_max_sh3,uint,16,8) [] = { 0x2000, 0x2000,
98 0x2000, 0x2000,
99 0x2000, 0x2000,
100 0x2000, 0x2000 };
101 VECT_VAR_DECL(expected_max_sh3,uint,32,4) [] = { 0x20000000, 0x20000000,
102 0x20000000, 0x20000000 };
103 VECT_VAR_DECL(expected_max_sh3,uint,64,2) [] = { 0x2000000000000000,
104 0x2000000000000000 };
105
106 /* Expected results with max input and shift by type width. */
107 VECT_VAR_DECL(expected_max_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
108 0x0, 0x0, 0x0, 0x0 };
109 VECT_VAR_DECL(expected_max_shmax,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
110 VECT_VAR_DECL(expected_max_shmax,int,32,2) [] = { 0x0, 0x0 };
111 VECT_VAR_DECL(expected_max_shmax,int,64,1) [] = { 0x0 };
112 VECT_VAR_DECL(expected_max_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
113 0x1, 0x1, 0x1, 0x1 };
114 VECT_VAR_DECL(expected_max_shmax,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
115 VECT_VAR_DECL(expected_max_shmax,uint,32,2) [] = { 0x1, 0x1 };
116 VECT_VAR_DECL(expected_max_shmax,uint,64,1) [] = { 0x1 };
117 VECT_VAR_DECL(expected_max_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
118 0x0, 0x0, 0x0, 0x0,
119 0x0, 0x0, 0x0, 0x0,
120 0x0, 0x0, 0x0, 0x0 };
121 VECT_VAR_DECL(expected_max_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
122 0x0, 0x0, 0x0, 0x0 };
123 VECT_VAR_DECL(expected_max_shmax,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
124 VECT_VAR_DECL(expected_max_shmax,int,64,2) [] = { 0x0, 0x0 };
125 VECT_VAR_DECL(expected_max_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
126 0x1, 0x1, 0x1, 0x1,
127 0x1, 0x1, 0x1, 0x1,
128 0x1, 0x1, 0x1, 0x1 };
129 VECT_VAR_DECL(expected_max_shmax,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
130 0x1, 0x1, 0x1, 0x1 };
131 VECT_VAR_DECL(expected_max_shmax,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
132 VECT_VAR_DECL(expected_max_shmax,uint,64,2) [] = { 0x1, 0x1 };
133
134 /* Expected results with min negative input and shift by 1. */
135 VECT_VAR_DECL(expected_min_sh1,int,8,8) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
136 0xc0, 0xc0, 0xc0, 0xc0 };
137 VECT_VAR_DECL(expected_min_sh1,int,16,4) [] = { 0xc000, 0xc000, 0xc000, 0xc000 };
138 VECT_VAR_DECL(expected_min_sh1,int,32,2) [] = { 0xc0000000, 0xc0000000 };
139 VECT_VAR_DECL(expected_min_sh1,int,64,1) [] = { 0xc000000000000000 };
140 VECT_VAR_DECL(expected_min_sh1,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
141 0x1, 0x1, 0x1, 0x1 };
142 VECT_VAR_DECL(expected_min_sh1,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
143 VECT_VAR_DECL(expected_min_sh1,uint,32,2) [] = { 0x1, 0x1 };
144 VECT_VAR_DECL(expected_min_sh1,uint,64,1) [] = { 0x1 };
145 VECT_VAR_DECL(expected_min_sh1,int,8,16) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
146 0xc0, 0xc0, 0xc0, 0xc0,
147 0xc0, 0xc0, 0xc0, 0xc0,
148 0xc0, 0xc0, 0xc0, 0xc0 };
149 VECT_VAR_DECL(expected_min_sh1,int,16,8) [] = { 0xc000, 0xc000, 0xc000, 0xc000,
150 0xc000, 0xc000, 0xc000, 0xc000 };
151 VECT_VAR_DECL(expected_min_sh1,int,32,4) [] = { 0xc0000000, 0xc0000000,
152 0xc0000000, 0xc0000000 };
153 VECT_VAR_DECL(expected_min_sh1,int,64,2) [] = { 0xc000000000000000,
154 0xc000000000000000 };
155 VECT_VAR_DECL(expected_min_sh1,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
156 0x1, 0x1, 0x1, 0x1,
157 0x1, 0x1, 0x1, 0x1,
158 0x1, 0x1, 0x1, 0x1 };
159 VECT_VAR_DECL(expected_min_sh1,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
160 0x1, 0x1, 0x1, 0x1 };
161 VECT_VAR_DECL(expected_min_sh1,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
162 VECT_VAR_DECL(expected_min_sh1,uint,64,2) [] = { 0x1, 0x1 };
163
164 /* Expected results with min negative input and shift by 3. */
165 VECT_VAR_DECL(expected_min_sh3,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
166 0xf0, 0xf0, 0xf0, 0xf0 };
167 VECT_VAR_DECL(expected_min_sh3,int,16,4) [] = { 0xf000, 0xf000, 0xf000, 0xf000 };
168 VECT_VAR_DECL(expected_min_sh3,int,32,2) [] = { 0xf0000000, 0xf0000000 };
169 VECT_VAR_DECL(expected_min_sh3,int,64,1) [] = { 0xf000000000000000 };
170 VECT_VAR_DECL(expected_min_sh3,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
171 0x1, 0x1, 0x1, 0x1 };
172 VECT_VAR_DECL(expected_min_sh3,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
173 VECT_VAR_DECL(expected_min_sh3,uint,32,2) [] = { 0x1, 0x1 };
174 VECT_VAR_DECL(expected_min_sh3,uint,64,1) [] = { 0x1 };
175 VECT_VAR_DECL(expected_min_sh3,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
176 0xf0, 0xf0, 0xf0, 0xf0,
177 0xf0, 0xf0, 0xf0, 0xf0,
178 0xf0, 0xf0, 0xf0, 0xf0 };
179 VECT_VAR_DECL(expected_min_sh3,int,16,8) [] = { 0xf000, 0xf000, 0xf000, 0xf000,
180 0xf000, 0xf000, 0xf000, 0xf000 };
181 VECT_VAR_DECL(expected_min_sh3,int,32,4) [] = { 0xf0000000, 0xf0000000,
182 0xf0000000, 0xf0000000 };
183 VECT_VAR_DECL(expected_min_sh3,int,64,2) [] = { 0xf000000000000000,
184 0xf000000000000000 };
185 VECT_VAR_DECL(expected_min_sh3,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
186 0x1, 0x1, 0x1, 0x1,
187 0x1, 0x1, 0x1, 0x1,
188 0x1, 0x1, 0x1, 0x1 };
189 VECT_VAR_DECL(expected_min_sh3,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
190 0x1, 0x1, 0x1, 0x1 };
191 VECT_VAR_DECL(expected_min_sh3,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
192 VECT_VAR_DECL(expected_min_sh3,uint,64,2) [] = { 0x1, 0x1 };
193
194 /* Expected results with min negative input and shift by type width. */
195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
196 0x0, 0x0, 0x0, 0x0 };
197 VECT_VAR_DECL(expected_min_shmax,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 };
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 };
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
201 0x1, 0x1, 0x1, 0x1 };
202 VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 };
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 };
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
206 0x0, 0x0, 0x0, 0x0,
207 0x0, 0x0, 0x0, 0x0,
208 0x0, 0x0, 0x0, 0x0 };
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
210 0x0, 0x0, 0x0, 0x0 };
211 VECT_VAR_DECL(expected_min_shmax,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 };
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
214 0x1, 0x1, 0x1, 0x1,
215 0x1, 0x1, 0x1, 0x1,
216 0x1, 0x1, 0x1, 0x1 };
217 VECT_VAR_DECL(expected_min_shmax,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
218 0x1, 0x1, 0x1, 0x1 };
219 VECT_VAR_DECL(expected_min_shmax,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
220 VECT_VAR_DECL(expected_min_shmax,uint,64,2) [] = { 0x1, 0x1 };
221
222 #define TEST_MSG "VRSRA_N"
223 void exec_vrsra_n (void)
224 {
225 /* Basic test: y=vrsra_n(x,v), then store the result. */
226 #define TEST_VRSRA_N(Q, T1, T2, W, N, V) \
227 VECT_VAR(vector_res, T1, W, N) = \
228 vrsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
229 VECT_VAR(vector2, T1, W, N), \
230 V); \
231 vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
232
233 DECL_VARIABLE_ALL_VARIANTS(vector);
234 DECL_VARIABLE_ALL_VARIANTS(vector2);
235 DECL_VARIABLE_ALL_VARIANTS(vector_res);
236
237 clean_results ();
238
239 /* Initialize input "vector" from "buffer". */
240 TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
241
242 /* Choose arbitrary initialization values. */
243 VDUP(vector2, , int, s, 8, 8, 0x11);
244 VDUP(vector2, , int, s, 16, 4, 0x22);
245 VDUP(vector2, , int, s, 32, 2, 0x33);
246 VDUP(vector2, , int, s, 64, 1, 0x44);
247 VDUP(vector2, , uint, u, 8, 8, 0x55);
248 VDUP(vector2, , uint, u, 16, 4, 0x66);
249 VDUP(vector2, , uint, u, 32, 2, 0x77);
250 VDUP(vector2, , uint, u, 64, 1, 0x88);
251
252 VDUP(vector2, q, int, s, 8, 16, 0x11);
253 VDUP(vector2, q, int, s, 16, 8, 0x22);
254 VDUP(vector2, q, int, s, 32, 4, 0x33);
255 VDUP(vector2, q, int, s, 64, 2, 0x44);
256 VDUP(vector2, q, uint, u, 8, 16, 0x55);
257 VDUP(vector2, q, uint, u, 16, 8, 0x66);
258 VDUP(vector2, q, uint, u, 32, 4, 0x77);
259 VDUP(vector2, q, uint, u, 64, 2, 0x88);
260
261 /* Choose shift amount arbitrarily. */
262 TEST_VRSRA_N(, int, s, 8, 8, 1);
263 TEST_VRSRA_N(, int, s, 16, 4, 12);
264 TEST_VRSRA_N(, int, s, 32, 2, 2);
265 TEST_VRSRA_N(, int, s, 64, 1, 32);
266 TEST_VRSRA_N(, uint, u, 8, 8, 2);
267 TEST_VRSRA_N(, uint, u, 16, 4, 3);
268 TEST_VRSRA_N(, uint, u, 32, 2, 5);
269 TEST_VRSRA_N(, uint, u, 64, 1, 33);
270
271 TEST_VRSRA_N(q, int, s, 8, 16, 1);
272 TEST_VRSRA_N(q, int, s, 16, 8, 12);
273 TEST_VRSRA_N(q, int, s, 32, 4, 2);
274 TEST_VRSRA_N(q, int, s, 64, 2, 32);
275 TEST_VRSRA_N(q, uint, u, 8, 16, 2);
276 TEST_VRSRA_N(q, uint, u, 16, 8, 3);
277 TEST_VRSRA_N(q, uint, u, 32, 4, 5);
278 TEST_VRSRA_N(q, uint, u, 64, 2, 33);
279
280 #define CMT ""
281 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
282 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
283 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
284 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
285 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
286 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
287 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
288 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
289 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
290 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
291 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
292 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
293 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
294 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
295 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
296 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
297
298
299 /* Initialize the accumulator with 0. */
300 VDUP(vector, , int, s, 8, 8, 0);
301 VDUP(vector, , int, s, 16, 4, 0);
302 VDUP(vector, , int, s, 32, 2, 0);
303 VDUP(vector, , int, s, 64, 1, 0);
304 VDUP(vector, , uint, u, 8, 8, 0);
305 VDUP(vector, , uint, u, 16, 4, 0);
306 VDUP(vector, , uint, u, 32, 2, 0);
307 VDUP(vector, , uint, u, 64, 1, 0);
308 VDUP(vector, q, int, s, 8, 16, 0);
309 VDUP(vector, q, int, s, 16, 8, 0);
310 VDUP(vector, q, int, s, 32, 4, 0);
311 VDUP(vector, q, int, s, 64, 2, 0);
312 VDUP(vector, q, uint, u, 8, 16, 0);
313 VDUP(vector, q, uint, u, 16, 8, 0);
314 VDUP(vector, q, uint, u, 32, 4, 0);
315 VDUP(vector, q, uint, u, 64, 2, 0);
316
317 /* Initialize with max values to check overflow. */
318 VDUP(vector2, , int, s, 8, 8, 0x7F);
319 VDUP(vector2, , int, s, 16, 4, 0x7FFF);
320 VDUP(vector2, , int, s, 32, 2, 0x7FFFFFFF);
321 VDUP(vector2, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL);
322 VDUP(vector2, , uint, u, 8, 8, 0xFF);
323 VDUP(vector2, , uint, u, 16, 4, 0xFFFF);
324 VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFFF);
325 VDUP(vector2, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
326 VDUP(vector2, q, int, s, 8, 16, 0x7F);
327 VDUP(vector2, q, int, s, 16, 8, 0x7FFF);
328 VDUP(vector2, q, int, s, 32, 4, 0x7FFFFFFF);
329 VDUP(vector2, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
330 VDUP(vector2, q, uint, u, 8, 16, 0xFF);
331 VDUP(vector2, q, uint, u, 16, 8, 0xFFFF);
332 VDUP(vector2, q, uint, u, 32, 4, 0xFFFFFFFF);
333 VDUP(vector2, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
334
335 /* Shift by 1 to check overflow with rounding constant. */
336 TEST_VRSRA_N(, int, s, 8, 8, 1);
337 TEST_VRSRA_N(, int, s, 16, 4, 1);
338 TEST_VRSRA_N(, int, s, 32, 2, 1);
339 TEST_VRSRA_N(, int, s, 64, 1, 1);
340 TEST_VRSRA_N(, uint, u, 8, 8, 1);
341 TEST_VRSRA_N(, uint, u, 16, 4, 1);
342 TEST_VRSRA_N(, uint, u, 32, 2, 1);
343 TEST_VRSRA_N(, uint, u, 64, 1, 1);
344 TEST_VRSRA_N(q, int, s, 8, 16, 1);
345 TEST_VRSRA_N(q, int, s, 16, 8, 1);
346 TEST_VRSRA_N(q, int, s, 32, 4, 1);
347 TEST_VRSRA_N(q, int, s, 64, 2, 1);
348 TEST_VRSRA_N(q, uint, u, 8, 16, 1);
349 TEST_VRSRA_N(q, uint, u, 16, 8, 1);
350 TEST_VRSRA_N(q, uint, u, 32, 4, 1);
351 TEST_VRSRA_N(q, uint, u, 64, 2, 1);
352
353 #undef CMT
354 #define CMT " (checking overflow: shift by 1, max input)"
355 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh1, CMT);
356 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh1, CMT);
357 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh1, CMT);
358 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh1, CMT);
359 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh1, CMT);
360 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh1, CMT);
361 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh1, CMT);
362 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh1, CMT);
363 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh1, CMT);
364 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh1, CMT);
365 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh1, CMT);
366 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh1, CMT);
367 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh1, CMT);
368 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh1, CMT);
369 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh1, CMT);
370 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh1, CMT);
371
372
373 /* Shift by 3 to check overflow with rounding constant. */
374 TEST_VRSRA_N(, int, s, 8, 8, 3);
375 TEST_VRSRA_N(, int, s, 16, 4, 3);
376 TEST_VRSRA_N(, int, s, 32, 2, 3);
377 TEST_VRSRA_N(, int, s, 64, 1, 3);
378 TEST_VRSRA_N(, uint, u, 8, 8, 3);
379 TEST_VRSRA_N(, uint, u, 16, 4, 3);
380 TEST_VRSRA_N(, uint, u, 32, 2, 3);
381 TEST_VRSRA_N(, uint, u, 64, 1, 3);
382 TEST_VRSRA_N(q, int, s, 8, 16, 3);
383 TEST_VRSRA_N(q, int, s, 16, 8, 3);
384 TEST_VRSRA_N(q, int, s, 32, 4, 3);
385 TEST_VRSRA_N(q, int, s, 64, 2, 3);
386 TEST_VRSRA_N(q, uint, u, 8, 16, 3);
387 TEST_VRSRA_N(q, uint, u, 16, 8, 3);
388 TEST_VRSRA_N(q, uint, u, 32, 4, 3);
389 TEST_VRSRA_N(q, uint, u, 64, 2, 3);
390
391 #undef CMT
392 #define CMT " (checking overflow: shift by 3, max input)"
393 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh3, CMT);
394 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh3, CMT);
395 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh3, CMT);
396 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh3, CMT);
397 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh3, CMT);
398 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh3, CMT);
399 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh3, CMT);
400 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh3, CMT);
401 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh3, CMT);
402 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh3, CMT);
403 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh3, CMT);
404 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh3, CMT);
405 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh3, CMT);
406 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh3, CMT);
407 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh3, CMT);
408 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh3, CMT);
409
410
411 /* Shift by max to check overflow with rounding constant. */
412 TEST_VRSRA_N(, int, s, 8, 8, 8);
413 TEST_VRSRA_N(, int, s, 16, 4, 16);
414 TEST_VRSRA_N(, int, s, 32, 2, 32);
415 TEST_VRSRA_N(, int, s, 64, 1, 64);
416 TEST_VRSRA_N(, uint, u, 8, 8, 8);
417 TEST_VRSRA_N(, uint, u, 16, 4, 16);
418 TEST_VRSRA_N(, uint, u, 32, 2, 32);
419 TEST_VRSRA_N(, uint, u, 64, 1, 64);
420 TEST_VRSRA_N(q, int, s, 8, 16, 8);
421 TEST_VRSRA_N(q, int, s, 16, 8, 16);
422 TEST_VRSRA_N(q, int, s, 32, 4, 32);
423 TEST_VRSRA_N(q, int, s, 64, 2, 64);
424 TEST_VRSRA_N(q, uint, u, 8, 16, 8);
425 TEST_VRSRA_N(q, uint, u, 16, 8, 16);
426 TEST_VRSRA_N(q, uint, u, 32, 4, 32);
427 TEST_VRSRA_N(q, uint, u, 64, 2, 64);
428
429 #undef CMT
430 #define CMT " (checking overflow: shift by max, max input)"
431 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_shmax, CMT);
432 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_shmax, CMT);
433 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_shmax, CMT);
434 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_shmax, CMT);
435 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_shmax, CMT);
436 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shmax, CMT);
437 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shmax, CMT);
438 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shmax, CMT);
439 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shmax, CMT);
440 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shmax, CMT);
441 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shmax, CMT);
442 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_shmax, CMT);
443 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shmax, CMT);
444 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shmax, CMT);
445 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shmax, CMT);
446 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shmax, CMT);
447
448
449 /* Initialize with min values to check overflow. */
450 VDUP(vector2, , int, s, 8, 8, 0x80);
451 VDUP(vector2, , int, s, 16, 4, 0x8000);
452 VDUP(vector2, , int, s, 32, 2, 0x80000000);
453 VDUP(vector2, , int, s, 64, 1, 0x8000000000000000LL);
454 VDUP(vector2, q, int, s, 8, 16, 0x80);
455 VDUP(vector2, q, int, s, 16, 8, 0x8000);
456 VDUP(vector2, q, int, s, 32, 4, 0x80000000);
457 VDUP(vector2, q, int, s, 64, 2, 0x8000000000000000ULL);
458
459 /* Shift by 1 to check overflow with rounding constant. */
460 TEST_VRSRA_N(, int, s, 8, 8, 1);
461 TEST_VRSRA_N(, int, s, 16, 4, 1);
462 TEST_VRSRA_N(, int, s, 32, 2, 1);
463 TEST_VRSRA_N(, int, s, 64, 1, 1);
464 TEST_VRSRA_N(q, int, s, 8, 16, 1);
465 TEST_VRSRA_N(q, int, s, 16, 8, 1);
466 TEST_VRSRA_N(q, int, s, 32, 4, 1);
467 TEST_VRSRA_N(q, int, s, 64, 2, 1);
468
469 #undef CMT
470 #define CMT " (checking overflow: shift by 1, min negative input)"
471 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_sh1, CMT);
472 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_sh1, CMT);
473 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_sh1, CMT);
474 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_sh1, CMT);
475 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_sh1, CMT);
476 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_sh1, CMT);
477 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_sh1, CMT);
478 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_sh1, CMT);
479 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_sh1, CMT);
480 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_sh1, CMT);
481 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_sh1, CMT);
482 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_sh1, CMT);
483 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_sh1, CMT);
484 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_sh1, CMT);
485 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_sh1, CMT);
486 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_sh1, CMT);
487
488
489 /* Shift by 3 to check overflow with rounding constant. */
490 TEST_VRSRA_N(, int, s, 8, 8, 3);
491 TEST_VRSRA_N(, int, s, 16, 4, 3);
492 TEST_VRSRA_N(, int, s, 32, 2, 3);
493 TEST_VRSRA_N(, int, s, 64, 1, 3);
494 TEST_VRSRA_N(q, int, s, 8, 16, 3);
495 TEST_VRSRA_N(q, int, s, 16, 8, 3);
496 TEST_VRSRA_N(q, int, s, 32, 4, 3);
497 TEST_VRSRA_N(q, int, s, 64, 2, 3);
498
499 #undef CMT
500 #define CMT " (checking overflow: shift by 3, min negative input)"
501 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_sh3, CMT);
502 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_sh3, CMT);
503 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_sh3, CMT);
504 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_sh3, CMT);
505 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_sh3, CMT);
506 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_sh3, CMT);
507 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_sh3, CMT);
508 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_sh3, CMT);
509 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_sh3, CMT);
510 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_sh3, CMT);
511 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_sh3, CMT);
512 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_sh3, CMT);
513 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_sh3, CMT);
514 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_sh3, CMT);
515 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_sh3, CMT);
516 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_sh3, CMT);
517
518
519 /* Shift by max to check overflow with rounding constant. */
520 TEST_VRSRA_N(, int, s, 8, 8, 8);
521 TEST_VRSRA_N(, int, s, 16, 4, 16);
522 TEST_VRSRA_N(, int, s, 32, 2, 32);
523 TEST_VRSRA_N(, int, s, 64, 1, 64);
524 TEST_VRSRA_N(q, int, s, 8, 16, 8);
525 TEST_VRSRA_N(q, int, s, 16, 8, 16);
526 TEST_VRSRA_N(q, int, s, 32, 4, 32);
527 TEST_VRSRA_N(q, int, s, 64, 2, 64);
528
529 #undef CMT
530 #define CMT " (checking overflow: shift by max, min negative input)"
531 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_shmax, CMT);
532 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_shmax, CMT);
533 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_shmax, CMT);
534 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_shmax, CMT);
535 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_shmax, CMT);
536 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_shmax, CMT);
537 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_shmax, CMT);
538 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_shmax, CMT);
539 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_shmax, CMT);
540 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_shmax, CMT);
541 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_shmax, CMT);
542 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_shmax, CMT);
543 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_shmax, CMT);
544 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_shmax, CMT);
545 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_shmax, CMT);
546 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_shmax, CMT);
547 }
548
549 int main (void)
550 {
551 exec_vrsra_n ();
552 return 0;
553 }