(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
aarch64/
advsimd-intrinsics/
vrshrn_n.c
       1  #include <arm_neon.h>
       2  #include "arm-neon-ref.h"
       3  #include "compute-ref-data.h"
       4  
       5  /* Expected results with input=0.  */
       6  VECT_VAR_DECL(expected_0,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
       7  					 0x0, 0x0, 0x0, 0x0 };
       8  VECT_VAR_DECL(expected_0,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
       9  VECT_VAR_DECL(expected_0,int,32,2) [] = { 0x0, 0x0 };
      10  VECT_VAR_DECL(expected_0,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
      11  					  0x0, 0x0, 0x0, 0x0 };
      12  VECT_VAR_DECL(expected_0,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
      13  VECT_VAR_DECL(expected_0,uint,32,2) [] = { 0x0, 0x0 };
      14  
      15  /* Expected results.  */
      16  VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
      17  				       0xfa, 0xfb, 0xfb, 0xfc };
      18  VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff9, 0xfff9, 0xfffa };
      19  VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
      20  VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfc, 0xfc, 0xfd, 0xfd,
      21  					0xfd, 0xfd, 0xfe, 0xfe };
      22  VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe };
      23  VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffffe, 0xfffffffe };
      24  
      25  /* Expected results with large shift amount.  */
      26  VECT_VAR_DECL(expected_sh_large,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
      27  						0x0, 0x0, 0x0, 0x0 };
      28  VECT_VAR_DECL(expected_sh_large,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
      29  VECT_VAR_DECL(expected_sh_large,int,32,2) [] = { 0x0, 0x0 };
      30  VECT_VAR_DECL(expected_sh_large,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
      31  						 0x0, 0x0, 0x0, 0x0 };
      32  VECT_VAR_DECL(expected_sh_large,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
      33  VECT_VAR_DECL(expected_sh_large,uint,32,2) [] = { 0x0, 0x0 };
      34  
      35  #define TEST_MSG "VRSHRN_N"
      36  void exec_vrshrn_n (void)
      37  {
      38    /* Basic test: v2=vrshrn_n(v1,v), then store the result.  */
      39  #define TEST_VRSHRN_N(T1, T2, W, N, W2, V)				\
      40    VECT_VAR(vector_res, T1, W2, N) =					\
      41      vrshrn_n_##T2##W(VECT_VAR(vector, T1, W, N),			\
      42  		     V);						\
      43    vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
      44  
      45    /* vector is twice as large as vector_res.  */
      46    DECL_VARIABLE(vector, int, 16, 8);
      47    DECL_VARIABLE(vector, int, 32, 4);
      48    DECL_VARIABLE(vector, int, 64, 2);
      49    DECL_VARIABLE(vector, uint, 16, 8);
      50    DECL_VARIABLE(vector, uint, 32, 4);
      51    DECL_VARIABLE(vector, uint, 64, 2);
      52  
      53    DECL_VARIABLE(vector_res, int, 8, 8);
      54    DECL_VARIABLE(vector_res, int, 16, 4);
      55    DECL_VARIABLE(vector_res, int, 32, 2);
      56    DECL_VARIABLE(vector_res, uint, 8, 8);
      57    DECL_VARIABLE(vector_res, uint, 16, 4);
      58    DECL_VARIABLE(vector_res, uint, 32, 2);
      59  
      60    clean_results ();
      61  
      62    /* Fill input vector with 0, to check behavior on limits.  */
      63    VDUP(vector, q, int, s, 16, 8, 0);
      64    VDUP(vector, q, int, s, 32, 4, 0);
      65    VDUP(vector, q, int, s, 64, 2, 0);
      66    VDUP(vector, q, uint, u, 16, 8, 0);
      67    VDUP(vector, q, uint, u, 32, 4, 0);
      68    VDUP(vector, q, uint, u, 64, 2, 0);
      69  
      70    /* Choose shift amount arbitrarily.  */
      71    TEST_VRSHRN_N(int, s, 16, 8, 8, 1);
      72    TEST_VRSHRN_N(int, s, 32, 4, 16, 1);
      73    TEST_VRSHRN_N(int, s, 64, 2, 32, 2);
      74    TEST_VRSHRN_N(uint, u, 16, 8, 8, 2);
      75    TEST_VRSHRN_N(uint, u, 32, 4, 16, 3);
      76    TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
      77  
      78  #define CMT " (with input = 0)"
      79    CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0, CMT);
      80    CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0, CMT);
      81    CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0, CMT);
      82    CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0, CMT);
      83    CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0, CMT);
      84    CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0, CMT);
      85  
      86  
      87    /* Test again, with predefined input values.  */
      88    VLOAD(vector, buffer, q, int, s, 16, 8);
      89    VLOAD(vector, buffer, q, int, s, 32, 4);
      90    VLOAD(vector, buffer, q, int, s, 64, 2);
      91    VLOAD(vector, buffer, q, uint, u, 16, 8);
      92    VLOAD(vector, buffer, q, uint, u, 32, 4);
      93    VLOAD(vector, buffer, q, uint, u, 64, 2);
      94  
      95    /* Choose shift amount arbitrarily.  */
      96    TEST_VRSHRN_N(int, s, 16, 8, 8, 1);
      97    TEST_VRSHRN_N(int, s, 32, 4, 16, 1);
      98    TEST_VRSHRN_N(int, s, 64, 2, 32, 2);
      99    TEST_VRSHRN_N(uint, u, 16, 8, 8, 2);
     100    TEST_VRSHRN_N(uint, u, 32, 4, 16, 3);
     101    TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
     102  
     103  #undef CMT
     104  #define CMT ""
     105    CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
     106    CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
     107    CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
     108    CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
     109    CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
     110    CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
     111  
     112  
     113    /* Fill input arbitrary values.  */
     114    VDUP(vector, q, int, s, 16, 8, 30);
     115    VDUP(vector, q, int, s, 32, 4, 0);
     116    VDUP(vector, q, int, s, 64, 2, 0);
     117    VDUP(vector, q, uint, u, 16, 8, 0xFFF0);
     118    VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFF0);
     119    VDUP(vector, q, uint, u, 64, 2, 0);
     120  
     121    /* Choose large shift amount arbitrarily.  */
     122    TEST_VRSHRN_N(int, s, 16, 8, 8, 7);
     123    TEST_VRSHRN_N(int, s, 32, 4, 16, 14);
     124    TEST_VRSHRN_N(int, s, 64, 2, 32, 31);
     125    TEST_VRSHRN_N(uint, u, 16, 8, 8, 7);
     126    TEST_VRSHRN_N(uint, u, 32, 4, 16, 16);
     127    TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
     128  
     129  #undef CMT
     130  #define CMT " (with large shift amount)"
     131    CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_sh_large, CMT);
     132    CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_sh_large, CMT);
     133    CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_sh_large, CMT);
     134    CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh_large, CMT);
     135    CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh_large, CMT);
     136    CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh_large, CMT);
     137  }
     138  
     139  int main (void)
     140  {
     141    exec_vrshrn_n ();
     142    return 0;
     143  }