1 #include <arm_neon.h>
2 #include "arm-neon-ref.h"
3 #include "compute-ref-data.h"
4
5
6 /* Expected results with input=0. */
7 VECT_VAR_DECL(expected_0,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
8 0x0, 0x0, 0x0, 0x0 };
9 VECT_VAR_DECL(expected_0,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
10 VECT_VAR_DECL(expected_0,int,32,2) [] = { 0x0, 0x0 };
11 VECT_VAR_DECL(expected_0,int,64,1) [] = { 0x0 };
12 VECT_VAR_DECL(expected_0,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
13 0x0, 0x0, 0x0, 0x0 };
14 VECT_VAR_DECL(expected_0,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
15 VECT_VAR_DECL(expected_0,uint,32,2) [] = { 0x0, 0x0 };
16 VECT_VAR_DECL(expected_0,uint,64,1) [] = { 0x0 };
17 VECT_VAR_DECL(expected_0,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
18 0x0, 0x0, 0x0, 0x0,
19 0x0, 0x0, 0x0, 0x0,
20 0x0, 0x0, 0x0, 0x0 };
21 VECT_VAR_DECL(expected_0,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
22 0x0, 0x0, 0x0, 0x0 };
23 VECT_VAR_DECL(expected_0,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
24 VECT_VAR_DECL(expected_0,int,64,2) [] = { 0x0, 0x0 };
25 VECT_VAR_DECL(expected_0,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
26 0x0, 0x0, 0x0, 0x0,
27 0x0, 0x0, 0x0, 0x0,
28 0x0, 0x0, 0x0, 0x0 };
29 VECT_VAR_DECL(expected_0,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
30 0x0, 0x0, 0x0, 0x0 };
31 VECT_VAR_DECL(expected_0,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
32 VECT_VAR_DECL(expected_0,uint,64,2) [] = { 0x0, 0x0 };
33
34 /* Expected results with input=0 and negative shift amount. */
35 VECT_VAR_DECL(expected_0_neg,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
36 0x0, 0x0, 0x0, 0x0 };
37 VECT_VAR_DECL(expected_0_neg,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
38 VECT_VAR_DECL(expected_0_neg,int,32,2) [] = { 0x0, 0x0 };
39 VECT_VAR_DECL(expected_0_neg,int,64,1) [] = { 0x0 };
40 VECT_VAR_DECL(expected_0_neg,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
41 0x0, 0x0, 0x0, 0x0 };
42 VECT_VAR_DECL(expected_0_neg,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
43 VECT_VAR_DECL(expected_0_neg,uint,32,2) [] = { 0x0, 0x0 };
44 VECT_VAR_DECL(expected_0_neg,uint,64,1) [] = { 0x0 };
45 VECT_VAR_DECL(expected_0_neg,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
46 0x0, 0x0, 0x0, 0x0,
47 0x0, 0x0, 0x0, 0x0,
48 0x0, 0x0, 0x0, 0x0 };
49 VECT_VAR_DECL(expected_0_neg,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
50 0x0, 0x0, 0x0, 0x0 };
51 VECT_VAR_DECL(expected_0_neg,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
52 VECT_VAR_DECL(expected_0_neg,int,64,2) [] = { 0x0, 0x0 };
53 VECT_VAR_DECL(expected_0_neg,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
54 0x0, 0x0, 0x0, 0x0,
55 0x0, 0x0, 0x0, 0x0,
56 0x0, 0x0, 0x0, 0x0 };
57 VECT_VAR_DECL(expected_0_neg,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
58 0x0, 0x0, 0x0, 0x0 };
59 VECT_VAR_DECL(expected_0_neg,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
60 VECT_VAR_DECL(expected_0_neg,uint,64,2) [] = { 0x0, 0x0 };
61
62 /* Expected results. */
63 VECT_VAR_DECL(expected,int,8,8) [] = { 0xe0, 0xe2, 0xe4, 0xe6,
64 0xe8, 0xea, 0xec, 0xee };
65 VECT_VAR_DECL(expected,int,16,4) [] = { 0xff80, 0xff88, 0xff90, 0xff98 };
66 VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff000, 0xfffff100 };
67 VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffffe };
68 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
69 0xff, 0xff, 0xff, 0xff };
70 VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
71 VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
72 VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffffffffffe };
73 VECT_VAR_DECL(expected,int,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
74 0x80, 0x80, 0x80, 0x80,
75 0x80, 0x80, 0x80, 0x80,
76 0x80, 0x80, 0x80, 0x80 };
77 VECT_VAR_DECL(expected,int,16,8) [] = { 0x8000, 0x8000, 0x8000, 0x8000,
78 0x8000, 0x8000, 0x8000, 0x8000 };
79 VECT_VAR_DECL(expected,int,32,4) [] = { 0x80000000, 0x80000000,
80 0x80000000, 0x80000000 };
81 VECT_VAR_DECL(expected,int,64,2) [] = { 0x8000000000000000,
82 0x8000000000000000 };
83 VECT_VAR_DECL(expected,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff,
84 0xff, 0xff, 0xff, 0xff,
85 0xff, 0xff, 0xff, 0xff,
86 0xff, 0xff, 0xff, 0xff };
87 VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
88 0xffff, 0xffff, 0xffff, 0xffff };
89 VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
90 0xffffffff, 0xffffffff };
91 VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffff,
92 0xffffffffffffffff };
93
94 /* Expected results with negative shift amount. */
95 VECT_VAR_DECL(expected_neg,int,8,8) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
96 0xfa, 0xfa, 0xfb, 0xfb };
97 VECT_VAR_DECL(expected_neg,int,16,4) [] = { 0xfffc, 0xfffc, 0xfffc, 0xfffc };
98 VECT_VAR_DECL(expected_neg,int,32,2) [] = { 0xfffffffe, 0xfffffffe };
99 VECT_VAR_DECL(expected_neg,int,64,1) [] = { 0xffffffffffffffff };
100 VECT_VAR_DECL(expected_neg,uint,8,8) [] = { 0x78, 0x78, 0x79, 0x79,
101 0x7a, 0x7a, 0x7b, 0x7b };
102 VECT_VAR_DECL(expected_neg,uint,16,4) [] = { 0x3ffc, 0x3ffc, 0x3ffc, 0x3ffc };
103 VECT_VAR_DECL(expected_neg,uint,32,2) [] = { 0x1ffffffe, 0x1ffffffe };
104 VECT_VAR_DECL(expected_neg,uint,64,1) [] = { 0xfffffffffffffff };
105 VECT_VAR_DECL(expected_neg,int,8,16) [] = { 0xff, 0xff, 0xff, 0xff,
106 0xff, 0xff, 0xff, 0xff,
107 0xff, 0xff, 0xff, 0xff,
108 0xff, 0xff, 0xff, 0xff };
109 VECT_VAR_DECL(expected_neg,int,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
110 0xffff, 0xffff, 0xffff, 0xffff };
111 VECT_VAR_DECL(expected_neg,int,32,4) [] = { 0xffffffff, 0xffffffff,
112 0xffffffff, 0xffffffff };
113 VECT_VAR_DECL(expected_neg,int,64,2) [] = { 0xffffffffffffffff,
114 0xffffffffffffffff };
115 VECT_VAR_DECL(expected_neg,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
116 0x1, 0x1, 0x1, 0x1,
117 0x1, 0x1, 0x1, 0x1,
118 0x1, 0x1, 0x1, 0x1 };
119 VECT_VAR_DECL(expected_neg,uint,16,8) [] = { 0x1f, 0x1f, 0x1f, 0x1f,
120 0x1f, 0x1f, 0x1f, 0x1f };
121 VECT_VAR_DECL(expected_neg,uint,32,4) [] = { 0x7ffff, 0x7ffff,
122 0x7ffff, 0x7ffff };
123 VECT_VAR_DECL(expected_neg,uint,64,2) [] = { 0xfffffffffff, 0xfffffffffff };
124
125 /* Expected results with negative input and large shift amount. */
126 VECT_VAR_DECL(expected_neg_large,int,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
127 0x80, 0x80, 0x80, 0x80 };
128 VECT_VAR_DECL(expected_neg_large,int,16,4) [] = { 0x8000, 0x8000,
129 0x8000, 0x8000 };
130 VECT_VAR_DECL(expected_neg_large,int,32,2) [] = { 0x80000000, 0x80000000 };
131 VECT_VAR_DECL(expected_neg_large,int,64,1) [] = { 0x8000000000000000 };
132 VECT_VAR_DECL(expected_neg_large,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
133 0xff, 0xff, 0xff, 0xff };
134 VECT_VAR_DECL(expected_neg_large,uint,16,4) [] = { 0xffff, 0xffff,
135 0xffff, 0xffff };
136 VECT_VAR_DECL(expected_neg_large,uint,32,2) [] = { 0xffffffff, 0xffffffff };
137 VECT_VAR_DECL(expected_neg_large,uint,64,1) [] = { 0xffffffffffffffff };
138 VECT_VAR_DECL(expected_neg_large,int,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
139 0x80, 0x80, 0x80, 0x80,
140 0x80, 0x80, 0x80, 0x80,
141 0x80, 0x80, 0x80, 0x80 };
142 VECT_VAR_DECL(expected_neg_large,int,16,8) [] = { 0x8000, 0x8000,
143 0x8000, 0x8000,
144 0x8000, 0x8000,
145 0x8000, 0x8000 };
146 VECT_VAR_DECL(expected_neg_large,int,32,4) [] = { 0x80000000, 0x80000000,
147 0x80000000, 0x80000000 };
148 VECT_VAR_DECL(expected_neg_large,int,64,2) [] = { 0x8000000000000000,
149 0x8000000000000000 };
150 VECT_VAR_DECL(expected_neg_large,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff,
151 0xff, 0xff, 0xff, 0xff,
152 0xff, 0xff, 0xff, 0xff,
153 0xff, 0xff, 0xff, 0xff };
154 VECT_VAR_DECL(expected_neg_large,uint,16,8) [] = { 0xffff, 0xffff,
155 0xffff, 0xffff,
156 0xffff, 0xffff,
157 0xffff, 0xffff };
158 VECT_VAR_DECL(expected_neg_large,uint,32,4) [] = { 0xffffffff, 0xffffffff,
159 0xffffffff, 0xffffffff };
160 VECT_VAR_DECL(expected_neg_large,uint,64,2) [] = { 0xffffffffffffffff,
161 0xffffffffffffffff };
162
163 /* Expected results with max input and shift by -1. */
164 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f,
165 0x3f, 0x3f, 0x3f, 0x3f };
166 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff,
167 0x3fff, 0x3fff };
168 VECT_VAR_DECL(expected_max_minus1,int,32,2) [] = { 0x3fffffff, 0x3fffffff };
169 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff };
170 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
171 0x7f, 0x7f, 0x7f, 0x7f };
172 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff,
173 0x7fff, 0x7fff };
174 VECT_VAR_DECL(expected_max_minus1,uint,32,2) [] = { 0x7fffffff, 0x7fffffff };
175 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff };
176 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f,
177 0x3f, 0x3f, 0x3f, 0x3f,
178 0x3f, 0x3f, 0x3f, 0x3f,
179 0x3f, 0x3f, 0x3f, 0x3f };
180 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff,
181 0x3fff, 0x3fff,
182 0x3fff, 0x3fff,
183 0x3fff, 0x3fff };
184 VECT_VAR_DECL(expected_max_minus1,int,32,4) [] = { 0x3fffffff, 0x3fffffff,
185 0x3fffffff, 0x3fffffff };
186 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff,
187 0x3fffffffffffffff };
188 VECT_VAR_DECL(expected_max_minus1,uint,8,16) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
189 0x7f, 0x7f, 0x7f, 0x7f,
190 0x7f, 0x7f, 0x7f, 0x7f,
191 0x7f, 0x7f, 0x7f, 0x7f };
192 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff,
193 0x7fff, 0x7fff,
194 0x7fff, 0x7fff,
195 0x7fff, 0x7fff };
196 VECT_VAR_DECL(expected_max_minus1,uint,32,4) [] = { 0x7fffffff, 0x7fffffff,
197 0x7fffffff, 0x7fffffff };
198 VECT_VAR_DECL(expected_max_minus1,uint,64,2) [] = { 0x7fffffffffffffff,
199 0x7fffffffffffffff };
200
201 /* Expected results with max input and large shift amount. */
202 VECT_VAR_DECL(expected_max_large,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
203 0x7f, 0x7f, 0x7f, 0x7f };
204 VECT_VAR_DECL(expected_max_large,int,16,4) [] = { 0x7fff, 0x7fff,
205 0x7fff, 0x7fff };
206 VECT_VAR_DECL(expected_max_large,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
207 VECT_VAR_DECL(expected_max_large,int,64,1) [] = { 0x7fffffffffffffff };
208 VECT_VAR_DECL(expected_max_large,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
209 0xff, 0xff, 0xff, 0xff };
210 VECT_VAR_DECL(expected_max_large,uint,16,4) [] = { 0xffff, 0xffff,
211 0xffff, 0xffff };
212 VECT_VAR_DECL(expected_max_large,uint,32,2) [] = { 0xffffffff, 0xffffffff };
213 VECT_VAR_DECL(expected_max_large,uint,64,1) [] = { 0xffffffffffffffff };
214 VECT_VAR_DECL(expected_max_large,int,8,16) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
215 0x7f, 0x7f, 0x7f, 0x7f,
216 0x7f, 0x7f, 0x7f, 0x7f,
217 0x7f, 0x7f, 0x7f, 0x7f };
218 VECT_VAR_DECL(expected_max_large,int,16,8) [] = { 0x7fff, 0x7fff,
219 0x7fff, 0x7fff,
220 0x7fff, 0x7fff,
221 0x7fff, 0x7fff };
222 VECT_VAR_DECL(expected_max_large,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
223 0x7fffffff, 0x7fffffff };
224 VECT_VAR_DECL(expected_max_large,int,64,2) [] = { 0x7fffffffffffffff,
225 0x7fffffffffffffff };
226 VECT_VAR_DECL(expected_max_large,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff,
227 0xff, 0xff, 0xff, 0xff,
228 0xff, 0xff, 0xff, 0xff,
229 0xff, 0xff, 0xff, 0xff };
230 VECT_VAR_DECL(expected_max_large,uint,16,8) [] = { 0xffff, 0xffff,
231 0xffff, 0xffff,
232 0xffff, 0xffff,
233 0xffff, 0xffff };
234 VECT_VAR_DECL(expected_max_large,uint,32,4) [] = { 0xffffffff, 0xffffffff,
235 0xffffffff, 0xffffffff };
236 VECT_VAR_DECL(expected_max_large,uint,64,2) [] = { 0xffffffffffffffff,
237 0xffffffffffffffff };
238
239 /* Expected results with saturation on 64-bits values.. */
240 VECT_VAR_DECL(expected_64,int,64,1) [] = { 0x8000000000000000 };
241 VECT_VAR_DECL(expected_64,int,64,2) [] = { 0x7fffffffffffffff,
242 0x7fffffffffffffff };
243
244 #define INSN vqshl
245 #define TEST_MSG "VQSHL/VQSHLQ"
246
247 #define FNNAME1(NAME) void exec_ ## NAME (void)
248 #define FNNAME(NAME) FNNAME1(NAME)
249
250 FNNAME (INSN)
251 {
252 /* Basic test: v3=vqshl(v1,v2), then store the result. */
253 #define TEST_VQSHL2(INSN, T3, Q, T1, T2, W, N, CMT) \
254 Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
255 VECT_VAR(vector_res, T1, W, N) = \
256 INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
257 VECT_VAR(vector_shift, T3, W, N)); \
258 vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
259 VECT_VAR(vector_res, T1, W, N));
260
261 /* Two auxliary macros are necessary to expand INSN */
262 #define TEST_VQSHL1(INSN, T3, Q, T1, T2, W, N, CMT) \
263 TEST_VQSHL2(INSN, T3, Q, T1, T2, W, N, CMT)
264
265 #define TEST_VQSHL(T3, Q, T1, T2, W, N, CMT) \
266 TEST_VQSHL1(INSN, T3, Q, T1, T2, W, N, CMT)
267
268
269 DECL_VARIABLE_ALL_VARIANTS(vector);
270 DECL_VARIABLE_ALL_VARIANTS(vector_res);
271
272 DECL_VARIABLE_SIGNED_VARIANTS(vector_shift);
273
274 clean_results ();
275
276 /* Fill input vector with 0, to check saturation on limits. */
277 VDUP(vector, , int, s, 8, 8, 0);
278 VDUP(vector, , int, s, 16, 4, 0);
279 VDUP(vector, , int, s, 32, 2, 0);
280 VDUP(vector, , int, s, 64, 1, 0);
281 VDUP(vector, , uint, u, 8, 8, 0);
282 VDUP(vector, , uint, u, 16, 4, 0);
283 VDUP(vector, , uint, u, 32, 2, 0);
284 VDUP(vector, , uint, u, 64, 1, 0);
285 VDUP(vector, q, int, s, 8, 16, 0);
286 VDUP(vector, q, int, s, 16, 8, 0);
287 VDUP(vector, q, int, s, 32, 4, 0);
288 VDUP(vector, q, int, s, 64, 2, 0);
289 VDUP(vector, q, uint, u, 8, 16, 0);
290 VDUP(vector, q, uint, u, 16, 8, 0);
291 VDUP(vector, q, uint, u, 32, 4, 0);
292 VDUP(vector, q, uint, u, 64, 2, 0);
293
294 /* Choose init value arbitrarily, will be used as shift amount */
295 /* Use values equal or one-less-than the type width to check
296 behavior on limits. */
297
298 /* 64-bits vectors first. */
299 /* Shift 8-bits lanes by 7... */
300 VDUP(vector_shift, , int, s, 8, 8, 7);
301 /* ... except: lane 0 (by 6), lane 1 (by 8) and lane 2 (by 9). */
302 VSET_LANE(vector_shift, , int, s, 8, 8, 0, 6);
303 VSET_LANE(vector_shift, , int, s, 8, 8, 1, 8);
304 VSET_LANE(vector_shift, , int, s, 8, 8, 2, 9);
305
306 /* Shift 16-bits lanes by 15... */
307 VDUP(vector_shift, , int, s, 16, 4, 15);
308 /* ... except: lane 0 (by 14), lane 1 (by 16), and lane 2 (by 17). */
309 VSET_LANE(vector_shift, , int, s, 16, 4, 0, 14);
310 VSET_LANE(vector_shift, , int, s, 16, 4, 1, 16);
311 VSET_LANE(vector_shift, , int, s, 16, 4, 2, 17);
312
313 /* Shift 32-bits lanes by 31... */
314 VDUP(vector_shift, , int, s, 32, 2, 31);
315 /* ... except lane 1 (by 30). */
316 VSET_LANE(vector_shift, , int, s, 32, 2, 1, 30);
317
318 /* Shift 64 bits lane by 63. */
319 VDUP(vector_shift, , int, s, 64, 1, 63);
320
321 /* 128-bits vectors. */
322 /* Shift 8-bits lanes by 8. */
323 VDUP(vector_shift, q, int, s, 8, 16, 8);
324 /* Shift 16-bits lanes by 16. */
325 VDUP(vector_shift, q, int, s, 16, 8, 16);
326 /* Shift 32-bits lanes by 32... */
327 VDUP(vector_shift, q, int, s, 32, 4, 32);
328 /* ... except lane 1 (by 33). */
329 VSET_LANE(vector_shift, q, int, s, 32, 4, 1, 33);
330
331 /* Shift 64-bits lanes by 64... */
332 VDUP(vector_shift, q, int, s, 64, 2, 64);
333 /* ... except lane 1 (by 62). */
334 VSET_LANE(vector_shift, q, int, s, 64, 2, 1, 62);
335
336 #define CMT " (with input = 0)"
337 TEST_VQSHL(int, , int, s, 8, 8, CMT);
338 TEST_VQSHL(int, , int, s, 16, 4, CMT);
339 TEST_VQSHL(int, , int, s, 32, 2, CMT);
340 TEST_VQSHL(int, , int, s, 64, 1, CMT);
341 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
342 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
343 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
344 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
345 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
346 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
347 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
348 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
349 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
350 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
351 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
352 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
353
354 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0, CMT);
355 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0, CMT);
356 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0, CMT);
357 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_0, CMT);
358 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0, CMT);
359 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0, CMT);
360 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0, CMT);
361 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_0, CMT);
362 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_0, CMT);
363 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_0, CMT);
364 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_0, CMT);
365 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_0, CMT);
366 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_0, CMT);
367 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_0, CMT);
368 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_0, CMT);
369 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_0, CMT);
370
371
372 /* Use negative shift amounts */
373 VDUP(vector_shift, , int, s, 8, 8, -1);
374 VDUP(vector_shift, , int, s, 16, 4, -2);
375 VDUP(vector_shift, , int, s, 32, 2, -3);
376 VDUP(vector_shift, , int, s, 64, 1, -4);
377 VDUP(vector_shift, q, int, s, 8, 16, -7);
378 VDUP(vector_shift, q, int, s, 16, 8, -11);
379 VDUP(vector_shift, q, int, s, 32, 4, -13);
380 VDUP(vector_shift, q, int, s, 64, 2, -20);
381
382 #undef CMT
383 #define CMT " (input 0 and negative shift amount)"
384 TEST_VQSHL(int, , int, s, 8, 8, CMT);
385 TEST_VQSHL(int, , int, s, 16, 4, CMT);
386 TEST_VQSHL(int, , int, s, 32, 2, CMT);
387 TEST_VQSHL(int, , int, s, 64, 1, CMT);
388 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
389 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
390 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
391 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
392 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
393 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
394 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
395 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
396 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
397 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
398 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
399 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
400
401 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0_neg, CMT);
402 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0_neg, CMT);
403 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0_neg, CMT);
404 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_0_neg, CMT);
405 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0_neg, CMT);
406 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0_neg, CMT);
407 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0_neg, CMT);
408 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_0_neg, CMT);
409 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_0_neg, CMT);
410 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_0_neg, CMT);
411 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_0_neg, CMT);
412 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_0_neg, CMT);
413 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_0_neg, CMT);
414 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_0_neg, CMT);
415 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_0_neg, CMT);
416 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_0_neg, CMT);
417
418 /* Test again, with predefined input values. */
419 TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
420
421 /* Choose init value arbitrarily, will be used as shift amount. */
422 VDUP(vector_shift, , int, s, 8, 8, 1);
423 VDUP(vector_shift, , int, s, 16, 4, 3);
424 VDUP(vector_shift, , int, s, 32, 2, 8);
425 VDUP(vector_shift, , int, s, 64, 1, -3);
426 VDUP(vector_shift, q, int, s, 8, 16, 10);
427 VDUP(vector_shift, q, int, s, 16, 8, 12);
428 VDUP(vector_shift, q, int, s, 32, 4, 32);
429 VDUP(vector_shift, q, int, s, 64, 2, 63);
430
431 #undef CMT
432 #define CMT ""
433 TEST_VQSHL(int, , int, s, 8, 8, CMT);
434 TEST_VQSHL(int, , int, s, 16, 4, CMT);
435 TEST_VQSHL(int, , int, s, 32, 2, CMT);
436 TEST_VQSHL(int, , int, s, 64, 1, CMT);
437 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
438 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
439 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
440 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
441 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
442 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
443 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
444 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
445 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
446 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
447 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
448 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
449
450 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
451 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
452 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
453 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
454 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
455 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
456 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
457 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
458 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
459 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
460 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
461 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
462 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
463 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
464 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
465 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
466
467
468 /* Use negative shift amounts */
469 VDUP(vector_shift, , int, s, 8, 8, -1);
470 VDUP(vector_shift, , int, s, 16, 4, -2);
471 VDUP(vector_shift, , int, s, 32, 2, -3);
472 VDUP(vector_shift, , int, s, 64, 1, -4);
473 VDUP(vector_shift, q, int, s, 8, 16, -7);
474 VDUP(vector_shift, q, int, s, 16, 8, -11);
475 VDUP(vector_shift, q, int, s, 32, 4, -13);
476 VDUP(vector_shift, q, int, s, 64, 2, -20);
477
478 #undef CMT
479 #define CMT " (negative shift amount)"
480 TEST_VQSHL(int, , int, s, 8, 8, CMT);
481 TEST_VQSHL(int, , int, s, 16, 4, CMT);
482 TEST_VQSHL(int, , int, s, 32, 2, CMT);
483 TEST_VQSHL(int, , int, s, 64, 1, CMT);
484 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
485 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
486 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
487 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
488 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
489 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
490 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
491 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
492 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
493 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
494 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
495 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
496
497 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_neg, CMT);
498 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_neg, CMT);
499 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_neg, CMT);
500 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_neg, CMT);
501 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_neg, CMT);
502 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_neg, CMT);
503 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_neg, CMT);
504 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_neg, CMT);
505 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_neg, CMT);
506 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_neg, CMT);
507 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_neg, CMT);
508 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_neg, CMT);
509 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_neg, CMT);
510 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_neg, CMT);
511 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_neg, CMT);
512 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_neg, CMT);
513
514
515 /* Use large shift amounts. */
516 VDUP(vector_shift, , int, s, 8, 8, 8);
517 VDUP(vector_shift, , int, s, 16, 4, 16);
518 VDUP(vector_shift, , int, s, 32, 2, 32);
519 VDUP(vector_shift, , int, s, 64, 1, 64);
520 VDUP(vector_shift, q, int, s, 8, 16, 8);
521 VDUP(vector_shift, q, int, s, 16, 8, 16);
522 VDUP(vector_shift, q, int, s, 32, 4, 32);
523 VDUP(vector_shift, q, int, s, 64, 2, 64);
524
525 #undef CMT
526 #define CMT " (large shift amount, negative input)"
527 TEST_VQSHL(int, , int, s, 8, 8, CMT);
528 TEST_VQSHL(int, , int, s, 16, 4, CMT);
529 TEST_VQSHL(int, , int, s, 32, 2, CMT);
530 TEST_VQSHL(int, , int, s, 64, 1, CMT);
531 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
532 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
533 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
534 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
535 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
536 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
537 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
538 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
539 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
540 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
541 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
542 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
543
544 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_neg_large, CMT);
545 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_neg_large, CMT);
546 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_neg_large, CMT);
547 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_neg_large, CMT);
548 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_neg_large, CMT);
549 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_neg_large, CMT);
550 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_neg_large, CMT);
551 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_neg_large, CMT);
552 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_neg_large, CMT);
553 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_neg_large, CMT);
554 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_neg_large, CMT);
555 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_neg_large, CMT);
556 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_neg_large, CMT);
557 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_neg_large, CMT);
558 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_neg_large, CMT);
559 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_neg_large, CMT);
560
561
562 /* Fill input vector with max value, to check saturation on limits */
563 VDUP(vector, , int, s, 8, 8, 0x7F);
564 VDUP(vector, , int, s, 16, 4, 0x7FFF);
565 VDUP(vector, , int, s, 32, 2, 0x7FFFFFFF);
566 VDUP(vector, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL);
567 VDUP(vector, , uint, u, 8, 8, 0xFF);
568 VDUP(vector, , uint, u, 16, 4, 0xFFFF);
569 VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
570 VDUP(vector, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
571 VDUP(vector, q, int, s, 8, 16, 0x7F);
572 VDUP(vector, q, int, s, 16, 8, 0x7FFF);
573 VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF);
574 VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
575 VDUP(vector, q, uint, u, 8, 16, 0xFF);
576 VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
577 VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
578 VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
579
580 /* Shift by -1 */
581 VDUP(vector_shift, , int, s, 8, 8, -1);
582 VDUP(vector_shift, , int, s, 16, 4, -1);
583 VDUP(vector_shift, , int, s, 32, 2, -1);
584 VDUP(vector_shift, , int, s, 64, 1, -1);
585 VDUP(vector_shift, q, int, s, 8, 16, -1);
586 VDUP(vector_shift, q, int, s, 16, 8, -1);
587 VDUP(vector_shift, q, int, s, 32, 4, -1);
588 VDUP(vector_shift, q, int, s, 64, 2, -1);
589
590 #undef CMT
591 #define CMT " (max input, shift by -1)"
592 TEST_VQSHL(int, , int, s, 8, 8, CMT);
593 TEST_VQSHL(int, , int, s, 16, 4, CMT);
594 TEST_VQSHL(int, , int, s, 32, 2, CMT);
595 TEST_VQSHL(int, , int, s, 64, 1, CMT);
596 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
597 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
598 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
599 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
600 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
601 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
602 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
603 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
604 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
605 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
606 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
607 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
608
609 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_minus1, CMT);
610 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_minus1, CMT);
611 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_minus1, CMT);
612 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_minus1, CMT);
613 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_minus1, CMT);
614 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_minus1, CMT);
615 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_minus1, CMT);
616 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_minus1, CMT);
617 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_minus1, CMT);
618 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_minus1, CMT);
619 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_minus1, CMT);
620 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_minus1, CMT);
621 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_minus1, CMT);
622 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_minus1, CMT);
623 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_minus1, CMT);
624 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_minus1, CMT);
625
626
627 /* Use large shift amounts */
628 VDUP(vector_shift, , int, s, 8, 8, 8);
629 VDUP(vector_shift, , int, s, 16, 4, 16);
630 VDUP(vector_shift, , int, s, 32, 2, 32);
631 VDUP(vector_shift, , int, s, 64, 1, 64);
632 VDUP(vector_shift, q, int, s, 8, 16, 8);
633 VDUP(vector_shift, q, int, s, 16, 8, 16);
634 VDUP(vector_shift, q, int, s, 32, 4, 32);
635 VDUP(vector_shift, q, int, s, 64, 2, 64);
636
637 #undef CMT
638 #define CMT " (max input, large shift amount)"
639 TEST_VQSHL(int, , int, s, 8, 8, CMT);
640 TEST_VQSHL(int, , int, s, 16, 4, CMT);
641 TEST_VQSHL(int, , int, s, 32, 2, CMT);
642 TEST_VQSHL(int, , int, s, 64, 1, CMT);
643 TEST_VQSHL(int, , uint, u, 8, 8, CMT);
644 TEST_VQSHL(int, , uint, u, 16, 4, CMT);
645 TEST_VQSHL(int, , uint, u, 32, 2, CMT);
646 TEST_VQSHL(int, , uint, u, 64, 1, CMT);
647 TEST_VQSHL(int, q, int, s, 8, 16, CMT);
648 TEST_VQSHL(int, q, int, s, 16, 8, CMT);
649 TEST_VQSHL(int, q, int, s, 32, 4, CMT);
650 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
651 TEST_VQSHL(int, q, uint, u, 8, 16, CMT);
652 TEST_VQSHL(int, q, uint, u, 16, 8, CMT);
653 TEST_VQSHL(int, q, uint, u, 32, 4, CMT);
654 TEST_VQSHL(int, q, uint, u, 64, 2, CMT);
655
656 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_large, CMT);
657 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_large, CMT);
658 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_large, CMT);
659 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_large, CMT);
660 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_large, CMT);
661 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_large, CMT);
662 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_large, CMT);
663 CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_large, CMT);
664 CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_large, CMT);
665 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_large, CMT);
666 CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_large, CMT);
667 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_large, CMT);
668 CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_large, CMT);
669 CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_large, CMT);
670 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_large, CMT);
671 CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_large, CMT);
672
673
674 /* Check 64 bits saturation. */
675 VDUP(vector, , int, s, 64, 1, -10);
676 VDUP(vector_shift, , int, s, 64, 1, 64);
677 VDUP(vector, q, int, s, 64, 2, 10);
678 VDUP(vector_shift, q, int, s, 64, 2, 64);
679
680 #undef CMT
681 #define CMT " (check saturation on 64 bits)"
682 TEST_VQSHL(int, , int, s, 64, 1, CMT);
683 TEST_VQSHL(int, q, int, s, 64, 2, CMT);
684
685 CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_64, CMT);
686 CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_64, CMT);
687 }
688
689 int main (void)
690 {
691 exec_vqshl ();
692 return 0;
693 }