(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
aarch64/
advsimd-intrinsics/
vmulx_n_f16_1.c
       1  /* { dg-do run } */
       2  /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
       3  /* { dg-add-options arm_v8_2a_fp16_neon } */
       4  /* { dg-skip-if "" { arm*-*-* } } */
       5  
       6  #include <arm_neon.h>
       7  #include "arm-neon-ref.h"
       8  #include "compute-ref-data.h"
       9  
      10  #define FP16_C(a) ((__fp16) a)
      11  #define A FP16_C (13.4)
      12  #define B FP16_C (__builtin_inff ())
      13  #define C FP16_C (-34.8)
      14  #define D FP16_C (-__builtin_inff ())
      15  #define E FP16_C (-0.0)
      16  #define F FP16_C (19.1)
      17  #define G FP16_C (-4.8)
      18  #define H FP16_C (0.0)
      19  
      20  float16_t elemE = E;
      21  float16_t elemF = F;
      22  float16_t elemG = G;
      23  float16_t elemH = H;
      24  
      25  #define I FP16_C (0.7)
      26  #define J FP16_C (-78)
      27  #define K FP16_C (11.23)
      28  #define L FP16_C (98)
      29  #define M FP16_C (87.1)
      30  #define N FP16_C (-8)
      31  #define O FP16_C (-1.1)
      32  #define P FP16_C (-9.7)
      33  
      34  /* Expected results for vmulx_n.  */
      35  VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
      36    = { 0x8000 /* A * E.  */,
      37        0xC000 /* FP16_C (-2.0f).  */,
      38        0x0000 /* C * E.  */,
      39        0x4000 /* FP16_C (2.0f).  */ };
      40  
      41  VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
      42    = { 0x5BFF /* A * F.  */,
      43        0x7C00 /* B * F.  */,
      44        0xE131 /* C * F.  */,
      45        0xFC00 /* D * F.  */ };
      46  
      47  VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
      48    = { 0xD405 /* A * G.  */,
      49        0xFC00 /* B * G.  */,
      50        0x5939 /* C * G.  */,
      51        0x7C00 /* D * G.  */ };
      52  
      53  VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
      54    = { 0x0000 /* A * H.  */,
      55        0x4000 /* FP16_C (2.0f).  */,
      56        0x8000 /* C * H.  */,
      57        0xC000 /* FP16_C (-2.0f).  */ };
      58  
      59  VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
      60    = { 0x8000 /* A * E.  */,
      61        0xC000 /* FP16_C (-2.0f).  */,
      62        0x0000 /* C * E.  */,
      63        0x4000 /* FP16_C (2.0f).  */,
      64        0x8000 /* I * E.  */,
      65        0x0000 /* J * E.  */,
      66        0x8000 /* K * E.  */,
      67        0x8000 /* L * E.  */ };
      68  
      69  VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
      70    = { 0x5BFF /* A * F.  */,
      71        0x7C00 /* B * F.  */,
      72        0xE131 /* C * F.  */,
      73        0xFC00 /* D * F.  */,
      74        0x4AAF /* I * F.  */,
      75        0xE5D1 /* J * F.  */,
      76        0x5AB3 /* K * F.  */,
      77        0x674F /* L * F.  */ };
      78  
      79  VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
      80    = { 0xD405 /* A * G.  */,
      81        0xFC00 /* B * G.  */,
      82        0x5939 /* C * G.  */,
      83        0x7C00 /* D * G.  */,
      84        0xC2B9 /* I * G.  */,
      85        0x5DDA /* J * G.  */,
      86        0xD2BD /* K * G.  */,
      87        0xDF5A /* L * G.  */ };
      88  
      89  VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
      90    = { 0x0000 /* A * H.  */,
      91        0x4000 /* FP16_C (2.0f).  */,
      92        0x8000 /* C * H.  */,
      93        0xC000 /* FP16_C (-2.0f).  */,
      94        0x0000 /* I * H.  */,
      95        0x8000 /* J * H.  */,
      96        0x0000 /* K * H.  */,
      97        0x0000 /* L * H.  */ };
      98  
      99  void exec_vmulx_n_f16 (void)
     100  {
     101  #undef TEST_MSG
     102  #define TEST_MSG "VMULX_N (FP16)"
     103    clean_results ();
     104  
     105    DECL_VARIABLE (vsrc_1, float, 16, 4);
     106    VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
     107    VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
     108    DECL_VARIABLE (vector_res, float, 16, 4)
     109      = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemE);
     110    vst1_f16 (VECT_VAR (result, float, 16, 4),
     111  	    VECT_VAR (vector_res, float, 16, 4));
     112  
     113    CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
     114  
     115    VECT_VAR (vector_res, float, 16, 4)
     116      = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemF);
     117    vst1_f16 (VECT_VAR (result, float, 16, 4),
     118  	    VECT_VAR (vector_res, float, 16, 4));
     119  
     120    CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
     121  
     122    VECT_VAR (vector_res, float, 16, 4)
     123      = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemG);
     124    vst1_f16 (VECT_VAR (result, float, 16, 4),
     125  	    VECT_VAR (vector_res, float, 16, 4));
     126  
     127    CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
     128  
     129    VECT_VAR (vector_res, float, 16, 4)
     130      = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemH);
     131    vst1_f16 (VECT_VAR (result, float, 16, 4),
     132  	    VECT_VAR (vector_res, float, 16, 4));
     133  
     134    CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
     135  
     136  #undef TEST_MSG
     137  #define TEST_MSG "VMULXQ_N (FP16)"
     138    clean_results ();
     139  
     140    DECL_VARIABLE (vsrc_1, float, 16, 8);
     141    VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
     142    VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
     143    DECL_VARIABLE (vector_res, float, 16, 8)
     144      = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemE);
     145    vst1q_f16 (VECT_VAR (result, float, 16, 8),
     146  	     VECT_VAR (vector_res, float, 16, 8));
     147  
     148    CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
     149  
     150    VECT_VAR (vector_res, float, 16, 8)
     151      = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemF);
     152    vst1q_f16 (VECT_VAR (result, float, 16, 8),
     153  	     VECT_VAR (vector_res, float, 16, 8));
     154  
     155    CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
     156  
     157    VECT_VAR (vector_res, float, 16, 8)
     158      = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemG);
     159    vst1q_f16 (VECT_VAR (result, float, 16, 8),
     160  	     VECT_VAR (vector_res, float, 16, 8));
     161  
     162    CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
     163  
     164    VECT_VAR (vector_res, float, 16, 8)
     165      = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemH);
     166    vst1q_f16 (VECT_VAR (result, float, 16, 8),
     167  	     VECT_VAR (vector_res, float, 16, 8));
     168  
     169    CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
     170  }
     171  
     172  int
     173  main (void)
     174  {
     175    exec_vmulx_n_f16 ();
     176    return 0;
     177  }