1  /* This file tests an intrinsic which currently has only an f16 variant and that
       2     is only available when FP16 arithmetic instructions are supported.  */
       3  /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
       4  
       5  #define INSN_NAME vcgtz
       6  #define TEST_MSG "VCGTZ/VCGTZQ"
       7  
       8  #include "cmp_zero_op.inc"
       9  
      10  /* Expected results.  */
      11  #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
      12  VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
      13  VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
      14  						     0xffff, 0xffff,
      15  						     0xffff, 0xffff,
      16  						     0xffff, 0xffff };
      17  #endif
      18  
      19  /* Extra FP tests with special values (NaN, ....).  */
      20  #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
      21  VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
      22  VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
      23  VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
      24  						 0xffff, 0xffff };
      25  VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
      26  VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
      27  VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
      28  #endif